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mb9b520ta series 32 - b it a rm ? cortex ? - m 3 fm 3 microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 05661 rev. *d revised january 12, 2018 the mb9b520ta series are highly integrated 32 - bit microcontrollers dedicated for embedded controllers with low - power consumption mode and competitive cost . th ese s eries are based on the a rm ? cortex ? - m3 processor with on - chip flash memory and sram, and have peripheral functions such as various t imers, adcs , dac s and communication interfaces (usb, can, uart, c sio, i 2 c , lin ). the products which are described in this data sheet are placed in to type12 product categories in fm3 family peripheral manual. f eatures 32 - bit a rm ? cortex ? - m3 core ? processor version: r2p1 ? up to 60 mhz frequency operation ? integrated nested vectored interrupt controller (nvic): 1 nmi (non - maskable interrupt) and 48 peripheral interrupts and 16 priority levels ? 24 - bit system timer (sys tick): system timer for os task management on - chip memories [f lash memory] ? dual operation flash memory ? main area: ? up to 1.5 m bytes ( 1008 kbytes (rom0) + 512 kbytes (rom1) of u pper bank and 16 kbytes (rom0) of l ower bank) ? work area: ? 64 kbytes (rom1) of l ower bank ? read cycle: 0 wait - cycle ? security function for code protection [sram] this series on - chip sram is composed of two independent sram (sram0, sram1). sram0 is connected to i - code bus and d - code bus of cortex - m3 core. sram1 is connected to system bus. ? sram0: up to 9 6 kbytes ? sram1: up to 9 6 kbytes external bus i nterface ? supports sram, nor nand flash memory device ? up to 8 chip selects ? 8 - /16 - bit data width ? up to 25 - bit address bit ? maximum area size: up to 256 mbytes ? supports address/data multiplex ? supports external rdy function usb interface the usb interface is c omposed of device and host. pll for usb is built - in, usb clock can be generated by multiplication of main clock. [usb device ] ? usb2.0 full - speed supported ? max 6 endpoint supported ? endpoint 0 is control transfer ? endpoint 1, 2 can select bulk - transfer, interrupt - transfer or isochronous - transfer ? endpoint 3 to 5 can select bulk - transfer or interrupt - transfer ? endpoint 1 to 5 are comprised of double buffers. ? the size of ea ch e ndpoint is as follows. ? endpoint 0, 2 to 5 : 64 bytes ? endpoint 1 : 256 bytes [usb hos t] ? usb2.0 full/low - speed supported ? bulk - transfer, interrupt - transfer and isochronous - transfer support ? usb device connected/dis - connected automatic detection ? automatic processing of the in/out token handshake packet ? max 256 - byte packet - length supported ? wake - up function supported can interface ? compatible with can specification 2.0a/b ? maximum transfer rate: 1 mbps ? built - in 32 message buffer
document number: 002 - 05661 rev. *d page 2 of 131 mb9b520ta series multi - func tion serial interface ( max 16 c hannels ) ? 16 channels with 16 steps 9 - bit fifo ? operation mode is selectable from the followings for each channel. ? uart ? csio ? lin ? i 2 c [uart] ? full duplex double buffer ? selection with or without parity supported ? built - in dedicated baud rate generator ? external clock available as a serial clock ? hardware flow control: automatically contr ol the transmission/reception by cts/rts (only ch.4) ? various error detection functions available (parity errors, framing errors, and overrun errors) [csio] ? full duplex double buffer ? built - in dedicated baud rate generator ? overrun error detection function av ailable [lin] ? lin protocol rev.2.1 supported ? full duplex double buffer ? master/slave mode supported ? lin break field generation (can be changed to 13 to 16 - bit length) ? lin break delimiter generation (can be changed to 1 to 4 - bit length) ? various error detecti on functions available (parity errors, framing errors, and overrun errors) [i 2 c] standard - mode (max 100 kbps) / fast - mode (max 400 kbps) supported dma controller (8 channels ) the dma controller has an independent bus from the cpu, so cpu and dma controller can process simultaneously. ? 8 independently configured and operated channels ? transfer can be started by software or request from the built - in peripherals ? transfer address area: 32 - bit (4 gbytes) ? transfer mode: block transfer/burst transfer/deman d transfer ? transfer data type: byte/half - word/word ? transfer block count: 1 to 16 ? number of transfers: 1 to 65536 a/d converter (max 24 channels) [12 - bit a/d converter] ? successive approximation type ? built - in 2units ? conversion time: 1.0 s @ 2.7 v to 5.5v ? pri ority conversion available (priority at 2levels) ? scanning conversion mode ? built - in fifo for conversion data s torage (for scan conversion: 16 steps, for priority conversion: 4 steps) d/a converter (max 2 channels) ? r - 2r type ? 10 - bit resolution base timer (max 16 channels) operation mode is selectable from the followings for each channel. ? 16 - bit pwm timer ? 16 - bit ppg timer ? 16 - /32 - bit reload timer ? 16 - /32 - bit pwc timer
document number: 002 - 05661 rev. *d page 3 of 131 mb9b520ta series general - purpose i/o port this series can use its pins as general - purpose i/o ports when they are not used for external bus or peripherals. moreover, the port relocate function is built in. it can set which i/o port the peripheral function can be allocated to. ? capable of pull - up co ntrol per pin ? capable of reading pin level directly ? built - in the port relocate function ? up to 154 high - spee d general - purpose i/ o ports @ 176 pin package ? some ports are 5v tolerant. s ee 4 . list of pin functions and 5 . i/o circuit type to confirm the corr esponding pins. dual timer (32 - /16 - bit down counter) the dual timer consists of two programmable 32 - /16 - bit down counters. operation mode is selectable from the followings for each channel. ? free - running ? periodic (=reload) ? one - shot quadrature position/ revol ution counter (qprc) (max 2 channels) the quadrature position/revolution counter (qprc) is used to measure the position of the position encoder. moreover, it is possible to use as the up/down counter. ? the detection edge of the three external event input pins ain, bin and zin is configurable. ? 16 - bit position counter ? 16 - bit revolution counter ? two 16 - bit compare registers hdmi - cec/remote control reception (up to 2 channels) ? hdmi - cec transmission ? header block automatic transmission by judging signal free ? generating status interrupt by detecting arbitration lost ? generating start, eom, ack automatically to output cec transmission by setting 1 byte data ? generating transmission status interrupt when transmitting 1 block (1 byte data and eom/ack) ? hdmi - cec recep tion ? automatic ack reply function available ? line error detection function available ? remote control reception ? 4 bytes reception buffer ? repeat code detection function available multi - function timer the multi - function timer is composed of the following blocks. ? 1 6 - bit free - run timer 3 ch ? input capture 4 ch ? output compare 6 ch ? a/ d activation compare 2 ch ? waveform generator 3 ch ? 16 - bit ppg timer 3 ch the following function can be used to achieve the motor control. ? pwm signal output function ? dc chopper waveform output function ? dead time function ? input capture function ? a/d convertor activate function ? dtif (motor emergency stop) interrupt function real - time clock (rtc) the real - time clock can count year/month/day/hour/minute/second/a day of the week from 0 0 to 99. ? the interrupt function with specifying date and time (year/month/day/hour/minute.) is available. this function is also available by specifying only year, month , day, hour or minute. ? timer interrupt function after set time or each set time . ? capable of rewriting the time with continuing the time count. ? leap year automatic count is available. watch counter the watch co unter is used for wake up from s leep and t imer mode. interval timer: up to 64 s (max) @ sub clock : 32.768 khz external interrupt controller unit ? up to 32 ex ternal interrupt input pins @ 176 pin package ? include one non - maskable interrupt (nmi) input pin watchdog timer (2 channels) a watchdog timer can generate interrupts or a reset when a time - out value is reached. this series consists of two different watchdogs, a "hardware" watchdog and a "software" watchdog. the "hardware" watchdog ti mer is clocked by the built - in l ow - speed cr oscillator. therefore, the "hardware" watchdog is active in any low - power consumption modes except rtc, stop , deep s tandby rtc, deep s tandby stop modes.
document number: 002 - 05661 rev. *d page 4 of 131 mb9b520ta series crc (cyclic redundancy check) accelerator the crc accelerator calculates the crc which has a heavy software processing load, and achieves a reduction of the integrity check processing load for reception data and storage. ccitt crc 1 6 and ieee - 802.3 crc32 are supported. ? ccitt crc16 generator polynomial: 0x1021 ? ieee - 802.3 crc32 generator polynomial: 0x04c11db7 clock and reset [clocks] selectable from five clock sources (2 external oscillators, 2 built - in cr oscillators, and main pll). ? main clock: 4 mhz to 48 mhz ? sub clock: 32.768 khz ? built - in h igh - speed cr clock: 4 mhz ? built - in l ow - speed cr clock: 100 khz ? main pll clock [re sets] ? reset requests from initx pin ? power - on reset ? software reset ? watchdog timers reset ? low - voltage detection reset ? clock super visor reset clock super visor (csv) clocks generated by built - in cr oscillators are used to supervise abnormality of the externa l clocks. ? if external clock failure (clock stop) is detected, reset is asserted. ? if external frequency anomaly is detected, interrupt or reset is asserted. low - voltage detector (lvd) this series includes 2 - stage monitoring of voltage on the vcc pins. when the voltage falls below the voltage that has been set, low - voltage detector generates an interrupt or reset. ? lvd1: error reporting via interrupt ? lvd2: auto - reset operation low - power consumption mode six low - power consumption modes supported. ? sleep ? timer ? rtc ? stop ? deep s tandby rtc (selectable between keeping the value of ram and not) ? deep s tandby stop (selectable between keeping the value of ram and not) debug ? seria l wire jtag debug port (swj - dp) ? embedded trace macrocell (etm) unique id unique value of the device (41 - bits) is set. power supply wide range voltage: vcc = 2.7 v to 5.5 v : usbvc c = 3.0 v to 3.6 v (when usb is used) = 2.7 v to 5.5 v (when gpio is used)
document number: 002 - 05661 rev. *d page 5 of 131 mb9b520ta series contents 1. product lineup ................................ ................................ ................................ ................................ ................................ .. 7 2. packages ................................ ................................ ................................ ................................ ................................ ........... 8 3. pin assignment ................................ ................................ ................................ ................................ ................................ . 9 4. list of pin functions ................................ ................................ ................................ ................................ ....................... 12 5. i /o circuit type ................................ ................................ ................................ ................................ ................................ 45 6. handling precautions ................................ ................................ ................................ ................................ ..................... 50 6.1 precautions for product design ................................ ................................ ................................ ................................ ... 50 6.2 precautions for package mounting ................................ ................................ ................................ .............................. 51 6.3 precautions for use environment ................................ ................................ ................................ ................................ 52 7. handling devices ................................ ................................ ................................ ................................ ............................ 53 8. block diagram ................................ ................................ ................................ ................................ ................................ . 56 9. memory size ................................ ................................ ................................ ................................ ................................ .... 57 10. memory map ................................ ................................ ................................ ................................ ................................ .... 57 11. pin status in each cpu state ................................ ................................ ................................ ................................ ........ 60 12. electrical characteristics ................................ ................................ ................................ ................................ ............... 68 12.1 absolute maximum ratings ................................ ................................ ................................ ................................ ......... 68 12.2 recommended operating conditions ................................ ................................ ................................ .......................... 70 12.3 dc characteristics ................................ ................................ ................................ ................................ ....................... 71 12.3.1 current rating ................................ ................................ ................................ ................................ .............................. 71 12.3.2 pin characteristics ................................ ................................ ................................ ................................ ....................... 75 12.4 ac characteristics ................................ ................................ ................................ ................................ ....................... 76 12.4.1 main clock input characteristics ................................ ................................ ................................ ................................ .. 76 12.4.2 sub clock input characteristics ................................ ................................ ................................ ................................ ... 77 12.4.3 built - in cr oscillation characteristics ................................ ................................ ................................ .......................... 78 12.4.4 operating conditions of main and usb pll (in the case of using main clock for input of pll) ................................ ... 79 12.4.5 operating conditions of main pll (in the case of using built - in high - speed cr for input clo ck of main pll) .............. 79 12.4.6 reset input characteristics ................................ ................................ ................................ ................................ .......... 81 12.4.7 power - on reset timing ................................ ................................ ................................ ................................ ................ 81 12.4.8 external bus timing ................................ ................................ ................................ ................................ ..................... 82 12.4.9 base timer input timing ................................ ................................ ................................ ................................ .............. 91 12.4.10 csio/uart timing ................................ ................................ ................................ ................................ .................. 92 12.4.11 external input timing ................................ ................................ ................................ ................................ .............. 100 12.4.12 quadrature position/revolution counter timing ................................ ................................ ................................ ...... 101 12.4.13 i 2 c timing ................................ ................................ ................................ ................................ ............................... 103 12.4.14 etm timing ................................ ................................ ................................ ................................ ............................ 104 12.4.15 jtag timing ................................ ................................ ................................ ................................ ........................... 105 12.5 12 - bit a/d converter ................................ ................................ ................................ ................................ .................. 106 12 .6 10 - bit d/a converter ................................ ................................ ................................ ................................ .................. 109 12.7 usb characteristics ................................ ................................ ................................ ................................ .................. 110 12.8 low - voltage detection characteristics ................................ ................................ ................................ ...................... 114 12.8.1 low - voltage detection reset ................................ ................................ ................................ ................................ ..... 114 12.8.2 interrupt of low - voltage detection ................................ ................................ ................................ ............................. 115 12.9 flash memory write/erase characteristics ................................ ................................ ................................ ............... 116 12.9.1 write / erase time ................................ ................................ ................................ ................................ ....................... 116 12.9.2 write cycles and data hold time ................................ ................................ ................................ ................................ . 116 12.10 return time from low - power consumption mode ................................ ................................ ................................ .... 117
document number: 002 - 05661 rev. *d page 6 of 131 mb9b520ta series 12.10.1 return factor: interrupt/wkup ................................ ................................ ................................ ............................... 117 12.10.2 return factor: reset ................................ ................................ ................................ ................................ .............. 119 13. ordering information ................................ ................................ ................................ ................................ .................... 121 14. package dimensions ................................ ................................ ................................ ................................ .................... 122 15. errata ................................ ................................ ................................ ................................ ................................ .............. 125 15.1 part numbers affected ................................ ................................ ................................ ................................ .............. 125 15.2 qualification status ................................ ................................ ................................ ................................ .................... 125 15 .3 errata summary ................................ ................................ ................................ ................................ ........................ 125 15.4 errata detail ................................ ................................ ................................ ................................ .............................. 125 15.4.1 hdmi - cec polling message issue ................................ ................................ ................................ ............................. 125 16. major changes ................................ ................................ ................................ ................................ .............................. 127 document history ................................ ................................ ................................ ................................ ............................... 129 sale s, solutions, and legal information ................................ ................................ ................................ ........................... 131
document number: 002 - 05661 rev. *d page 7 of 131 mb9b520ta series 1. p roduct l ineup memory s ize product name mb9bf528sa/ta mb9bf 529sa/ta on - chip flash memory main area 1 m bytes 1.5 m bytes work area 64 kbytes 64 kbytes on - chip sram sram0 8 0 kbytes 96 kbytes sram1 8 0 kbytes 96 kbytes total 16 0 kbytes 192 kbytes function product name mb9bf528sa mb9bf529sa mb9bf528ta mb9bf529ta pin count 144 176/192 cpu cortex - m3 freq. 60 mhz power supply voltage range 2.7 v to 5.5 v usb2.0 ( device /host) 1 ch . can 1 ch. dmac 8 ch. external bus interface addr: 25 - bit (max) r/wdata : 8 - /16 - bit (max) cs: 8 (max) sram , nor flash memory , nand flash memory multi - function serial interface (uart/csio/lin/i 2 c) 16 ch. (max) with 16 steps9 - bit fifo base timer (pwc/reload timer/pwm/ppg) 16 ch. (max) mf timer a/d activation compare 2 ch. 1 unit input capture 4 ch. free - run timer 3 ch. output compare 6 ch. waveform generator 3 ch. ppg 3 ch. qprc 1 ch. (max) 2 ch. (max) dual timer 1 unit hdmi - cec/ remote control reception 2 ch. (max) real - time clock 1 unit watch counter 1 unit crc accelerator yes watchdog timer 1 ch. (sw) + 1 ch. (hw) external interrupts 32 pins (max) + nmi 1 i/o ports 122 p ins (max) 154 pins (max) 12 - bit a/d converter 24 ch . (2 unit s ) 10 - bit d/a converter 2 ch. (max) csv (clock super visor) yes lvd (low - voltage detector) 2 ch. built - in cr high - speed 4 mhz low - speed 100 khz debug function swj - dp / etm unique id yes note: ? all signals of the peripheral function in each product cannot be allocated by limiting the pins of package. it is necessary to use the port relocate function of the i/o port according to your function use. see 12 . electrical characteristics 12.4 . ac characteristics 12.4.3 . built - in cr oscillation characteristics for accuracy of built - in cr.
document number: 002 - 05661 rev. *d page 8 of 131 mb9b520ta series 2. packages product name package mb9bf528sa mb9bf529sa mb9bf52 8ta mb9bf529ta lqfp: lqs 144 (0.5 mm pitch) ? - lqep: lqp 176 (0.5 mm pitch) - ? bga: lbe 192 (0. 8 mm pitch) - ? ? : supported note: ? see 14 . package dimensions for detailed information on each package.
document number: 002 - 05661 rev. *d page 9 of 131 mb9b520ta series 3. pin assignment lqp 176 (top view) note : ? the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. vss p81/udp0 p80/udm0 usbvcc pf5/sck6_2/igtrg0_1/int08_0/wkup3/cec1_0 pf4/sot6_2/tiob06_0/int07_0 pf3/sin6_2/tioa06_0/int06_0 p60/sin5_0/tioa02_2/int15_1/wkup5/mad20_0 p61/uhconx/sot5_0/tiob02_2/mad19_0 p62/adtg_3/sck5_0/mad18_0 pd3/tiob03_2/mad17_0 pd2/sin4_0/tioa03_2/int00_2/mad16_0 pd1/sot4_0/tiob14_0/int31_1/mad15_0 pd0/sck4_0/tiob10_2/int30_1/mad14_0 pcf/cts4_0/tiob08_2/mad13_0 pce/rts4_0/tiob06_1/mad12_0 pcd/mad11_0 pcc/mad10_0 pcb/mad09_0 vss vcc pca/sck15_0/mad08_0 pc9/sot15_0/mad07_0 pc8/sin15_0/mad06_0 pc7/crout_1/rtcco_0/subout_0/mad05_0 pc6/sck14_0/tioa14_0/mad04_0 pc5/sot14_0/tioa10_2/mad03_0 pc4/sin14_0/tioa08_2/cec0_1/mad02_0 pc3/tioa06_1/mad01_0 pc2/sck13_0/mad00_0 pc1/da1_0/sot13_0/mcsx4_0 pc0/da0_0/sin13_0/mcsx5_0 p95/tiob13_0/int27_0 p94/sck5_1/tiob12_0/int26_0 p93/sot5_1/tiob11_0 p92/sin5_1/tiob10_0 p91/tiob09_0/int31_0 p90/tiob08_0/int30_0 p04/tdo/swo p03/tms/swdio p02/tdi p01/tck/swclk p00/trstx vcc 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 vcc 1 132 vss pa0/sin8_0/tioa08_0/mad21_0 2 131 vcc pa1/sot8_0/tioa09_0/mad22_0 3 130 p83/mcsx6_0 pa2/sck8_0/tioa10_0/mad23_0 4 129 p82/mcsx7_0 pa3/sin9_0/tioa11_0/mad24_0 5 128 pf6/nmix/wkup0 pa4/rx0_2/sot9_0/tioa12_0/int03_0 6 127 p20/ain1_1/int05_0/crout_0 pa5/tx0_2/sck9_0/tioa13_0/int10_2 7 126 p21/sin0_0/bin1_1/int06_1 p05/traced0/sin4_2/tioa05_2/int00_1 8 125 p22/an23/sot0_0/zin1_1/tiob07_1 p06/traced1/sot4_2/tiob05_2/int01_1 9 124 p23/an22/sck0_0/rto00_1/tioa07_1 p07/traced2/adtg_0/sck4_2 10 123 p24/an21/sin2_1/rto01_1/int01_2 p08/traced3/cts4_2/tioa00_2 11 122 p25/an20/sot2_1/rto02_1 p09/traceclk/rts4_2/tiob00_2 12 121 p26/an19/sck2_1/rto03_1 p50/sin3_1/ain0_2/int00_0/moex_0 13 120 p27/an18/sck12_0/rto04_1/int02_2 p51/sot3_1/bin0_2/int01_0/mwex_0 14 119 p28/an17/adtg_4/sot12_0/rto05_1/int09_0 p52/sck3_1/zin0_2/int02_0/mdqm0_0 15 118 p29/an16/sin12_0 p53/sin6_0/tioa01_2/int07_2/mdqm1_0 16 117 avrh p54/sot6_0/tiob01_2/male_0 17 116 avrl p55/adtg_1/sck6_0/mrdy_0 18 115 avss p56/sin1_0/tioa09_2/int08_2/cec1_1/mnale_0 19 114 avcc p57/sot1_0/tiob09_2/int16_1/mncle_0 20 113 pb7/tiob12_1/int23_0 p58/sck1_0/tioa11_2/int17_1/mnwex_0 21 112 pb6/sck0_2/tioa12_1/int22_0 p59/sin7_0/tiob11_2/int09_2/mnrex_0 22 111 pb5/sot0_2/tiob11_1/int21_0 p5a/sot7_0/tioa13_1/int18_1/mcsx0_0 23 110 pb4/sin0_2/tioa11_1/int20_0 p5b/sck7_0/tiob13_1/int19_1/mcsx1_0 24 109 pb3/tiob10_1/int19_0 p5c/tioa06_2/int28_0 25 108 pb2/sck7_2/tioa10_1/int18_0 p5d/tiob06_2/int29_0 26 107 pb1/sot7_2/tiob09_1/int17_0 vss 27 106 pb0/sin7_2/tioa09_1/int16_0 p30/ain0_0/tiob00_1/int03_2/wkup4 28 105 p1f/an15/adtg_5/frck0_1/tiob15_2/int29_1 p31/sck6_1/bin0_0/tiob01_1/int04_2 29 104 p1e/an14/rts4_1/dtti0x_1/tioa15_2/int28_1 p32/sot6_1/zin0_0/tiob02_1/int05_2 30 103 p1d/an13/cts4_1/ic03_1/tiob14_2/int27_1 p33/adtg_6/sin6_1/tiob03_1/int04_0 31 102 p1c/an12/sck4_1/ic02_1/tioa14_2/int26_1 p34/tx0_1/frck0_0/tiob04_1 32 101 p1b/an11/sot4_1/ic01_1/tiob13_2/int25_1 p35/rx0_1/ic03_0/tiob05_1/int08_1 33 100 p1a/an10/sin4_1/ic00_1/tioa13_2/int05_1 p36/sin5_2/ic02_0/tioa12_2/int09_1 34 99 p19/an09/sck2_2/int22_1 p37/sot5_2/ic01_0/tiob12_2/int10_1 35 98 p18/an08/sot2_2/int21_1 p38/sck5_2/ic00_0/int11_1 36 97 p17/an07/sin2_2/int04_1 p39/adtg_2/dtti0x_0/rtcco_2/subout_2 37 96 p16/an06/sck0_1/int20_1 p3a/rto00_0/tioa00_1 38 95 p15/an05/sot0_1/ic03_2 p3b/rto01_0/tioa01_1 39 94 p14/an04/sin0_1/ic02_2/int03_1 p3c/rto02_0/tioa02_1 40 93 p13/an03/sck1_1/ic01_2/rtcco_1/subout_1 p3d/rto03_0/tioa03_1 41 92 p12/an02/sot1_1/ic00_2 p3e/rto04_0/tioa04_1 42 91 p11/an01/sin1_1/frck0_2/int02_1/wkup1 p3f/rto05_0/tioa05_1 43 90 p10/an00 vss 44 89 vcc 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 vcc p40/sin10_0/tioa00_0/int12_1/mcsx2_0 p41/sot10_0/tioa01_0/int13_1/mcsx3_0 p42/sck10_0/tioa02_0/mclkout_0 p43/adtg_7/sin11_0/tioa03_0 p44/sot11_0/tioa04_0 p45/sck11_0/tioa05_0 c vss vcc p46/x0a p47/x1a initx p48/sin3_2/int14_1 p49/sot3_2/ain0_1/tiob00_0 p4a/sck3_2/bin0_1/tiob01_0/madata00_0 p4b/igtrg0_0/zin0_1/tiob02_0/madata01_0 p4c/sck7_1/ain1_2/tiob03_0/madata02_0 p4d/sot7_1/bin1_2/tiob04_0/madata03_0 p4e/sin7_1/zin1_2/tiob05_0/int06_2/madata04_0 p70/tx0_0/tioa04_2/madata05_0 p71/rx0_0/tiob04_2/int13_2/madata06_0 p72/sin2_0/int14_2/wkup2/madata07_0 p73/sot2_0/int15_2/madata08_0 p74/sck2_0/madata09_0 p75/adtg_8/sin3_0/int07_1/madata10_0 p76/sot3_0/tioa07_2/int11_2/madata11_0 p77/sck3_0/tiob07_2/int12_2/madata12_0 p78/ain1_0/tioa15_0/madata13_0 p79/bin1_0/tiob15_0/int23_1/madata14_0 p7a/zin1_0/int24_1/madata15_0 p7b/tiob07_0/int10_0 p7c/tioa07_0/int11_0 p7d/tioa14_1/int12_0 p7e/tiob14_1/int24_0 p7f/tioa15_1/int25_0 pf0/sin1_2/tiob15_1/int13_0/cec0_0 pf1/sot1_2/tioa08_1/int14_0 pf2/sck1_2/tiob08_1/int15_0 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 176
document number: 002 - 05661 rev. *d page 10 of 131 mb9b520ta series lqs 144 (top view) note : ? the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the p in. vss p81/udp0 p80/udm0 usbvcc pf5/igtrg0_1/int08_0/wkup3/cec1_0 p60/sin5_0/tioa02_2/int15_1/wkup5/mad20_0 p61/uhconx/sot5_0/tiob02_2/mad19_0 p62/adtg_3/sck5_0/mad18_0 pd3/tiob03_2/mad17_0 pd2/sin4_0/tioa03_2/int00_2/mad16_0 pd1/sot4_0/tiob14_0/int31_1/mad15_0 pd0/sck4_0/tiob10_2/int30_1/mad14_0 pcf/cts4_0/tiob08_2/mad13_0 pce/rts4_0/tiob06_1/mad12_0 pcd/mad11_0 pcc/mad10_0 pcb/mad09_0 vss vcc pca/sck15_0/mad08_0 pc9/sot15_0/mad07_0 pc8/sin15_0/mad06_0 pc7/crout_1/rtcco_0/subout_0/mad05_0 pc6/sck14_0/tioa14_0/mad04_0 pc5/sot14_0/tioa10_2/mad03_0 pc4/sin14_0/tioa08_2/cec0_1/mad02_0 pc3/tioa06_1/mad01_0 pc2/sck13_0/mad00_0 pc1/da1_0/sot13_0/mcsx4_0 pc0/da0_0/sin13_0/mcsx5_0 p04/tdo/swo p03/tms/swdio p02/tdi p01/tck/swclk p00/trstx vcc 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 vcc 1 108 vss pa0/sin8_0/tioa08_0/mad21_0 2 107 vcc pa1/sot8_0/tioa09_0/mad22_0 3 106 p83/mcsx6_0 pa2/sck8_0/tioa10_0/mad23_0 4 105 p82/mcsx7_0 pa3/sin9_0/tioa11_0/mad24_0 5 104 pf6/nmix/wkup0 pa4/rx0_2/sot9_0/tioa12_0/int03_0 6 103 p20/ain1_1/int05_0/crout_0 pa5/tx0_2/sck9_0/tioa13_0/int10_2 7 102 p21/sin0_0/bin1_1/int06_1 p05/traced0/sin4_2/tioa05_2/int00_1 8 101 p22/an23/sot0_0/zin1_1/tiob07_1 p06/traced1/sot4_2/tiob05_2/int01_1 9 100 p23/an22/sck0_0/rto00_1/tioa07_1 p07/traced2/adtg_0/sck4_2 10 99 p24/an21/sin2_1/rto01_1/int01_2 p08/traced3/cts4_2/tioa00_2 11 98 p25/an20/sot2_1/rto02_1 p09/traceclk/rts4_2/tiob00_2 12 97 p26/an19/sck2_1/rto03_1 p50/sin3_1/ain0_2/int00_0/moex_0 13 96 p27/an18/sck12_0/rto04_1/int02_2 p51/sot3_1/bin0_2/int01_0/mwex_0 14 95 p28/an17/adtg_4/sot12_0/rto05_1/int09_0 p52/sck3_1/zin0_2/int02_0/mdqm0_0 15 94 p29/an16/sin12_0 p53/sin6_0/tioa01_2/int07_2/mdqm1_0 16 93 avrh p54/sot6_0/tiob01_2/male_0 17 92 avrl p55/adtg_1/sck6_0/mrdy_0 18 91 avss p56/sin1_0/tioa09_2/int08_2/cec1_1/mnale_0 19 90 avcc p57/sot1_0/tiob09_2/int16_1/mncle_0 20 89 p1f/an15/adtg_5/frck0_1/tiob15_2/int29_1 p58/sck1_0/tioa11_2/int17_1/mnwex_0 21 88 p1e/an14/rts4_1/dtti0x_1/tioa15_2/int28_1 p59/sin7_0/tiob11_2/int09_2/mnrex_0 22 87 p1d/an13/cts4_1/ic03_1/tiob14_2/int27_1 p5a/sot7_0/tioa13_1/int18_1/mcsx0_0 23 86 p1c/an12/sck4_1/ic02_1/tioa14_2/int26_1 p5b/sck7_0/tiob13_1/int19_1/mcsx1_0 24 85 p1b/an11/sot4_1/ic01_1/tiob13_2/int25_1 vss 25 84 p1a/an10/sin4_1/ic00_1/tioa13_2/int05_1 p36/sin5_2/ic02_0/tioa12_2/int09_1 26 83 p19/an09/sck2_2/int22_1 p37/sot5_2/ic01_0/tiob12_2/int10_1 27 82 p18/an08/sot2_2/int21_1 p38/sck5_2/ic00_0/int11_1 28 81 p17/an07/sin2_2/int04_1 p39/adtg_2/dtti0x_0/rtcco_2/subout_2 29 80 p16/an06/sck0_1/int20_1 p3a/rto00_0/tioa00_1 30 79 p15/an05/sot0_1/ic03_2 p3b/rto01_0/tioa01_1 31 78 p14/an04/sin0_1/ic02_2/int03_1 p3c/rto02_0/tioa02_1 32 77 p13/an03/sck1_1/ic01_2/rtcco_1/subout_1 p3d/rto03_0/tioa03_1 33 76 p12/an02/sot1_1/ic00_2 p3e/rto04_0/tioa04_1 34 75 p11/an01/sin1_1/frck0_2/int02_1/wkup1 p3f/rto05_0/tioa05_1 35 74 p10/an00 vss 36 73 vcc 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 vcc p40/sin10_0/tioa00_0/int12_1/mcsx2_0 p41/sot10_0/tioa01_0/int13_1/mcsx3_0 p42/sck10_0/tioa02_0/mclkout_0 p43/adtg_7/sin11_0/tioa03_0 p44/sot11_0/tioa04_0 p45/sck11_0/tioa05_0 c vss vcc p46/x0a p47/x1a initx p48/sin3_2/int14_1 p49/sot3_2/ain0_1/tiob00_0 p4a/sck3_2/bin0_1/tiob01_0/madata00_0 p4b/igtrg0_0/zin0_1/tiob02_0/madata01_0 p4c/sck7_1/ain1_2/tiob03_0/madata02_0 p4d/sot7_1/bin1_2/tiob04_0/madata03_0 p4e/sin7_1/zin1_2/tiob05_0/int06_2/madata04_0 p70/tx0_0/tioa04_2/madata05_0 p71/rx0_0/tiob04_2/int13_2/madata06_0 p72/sin2_0/int14_2/wkup2/madata07_0 p73/sot2_0/int15_2/madata08_0 p74/sck2_0/madata09_0 p75/adtg_8/sin3_0/int07_1/madata10_0 p76/sot3_0/tioa07_2/int11_2/madata11_0 p77/sck3_0/tiob07_2/int12_2/madata12_0 p78/ain1_0/tioa15_0/madata13_0 p79/bin1_0/tiob15_0/int23_1/madata14_0 p7a/zin1_0/int24_1/madata15_0 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 144
document number: 002 - 05661 rev. *d page 11 of 131 mb9b520ta series lbe 192 (top view) note : ? the number after the underscore ( " _ " ) in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a udp0 udm0 usb vcc vss pcd pcb vss vcc pc8 vss tck vcc b vss pa0 pf5 pf3 p61 pd1 pca pc1 p95 p92 tdo tms trstx vss c vcc pa1 pa2 pf4 p60 pd2 pcc pc5 pc0 p93 p90 tdi pf6 vcc d pa5 pa4 p05 p06 pa3 pd3 pce pc6 pc2 p94 p91 p21 p20 p83 e vss p07 p08 p09 p50 p62 pcf pc7 pc3 p25 p24 p23 p22 p82 f p51 p52 p53 p54 p55 p56 pd0 pc9 pc4 p29 p28 p27 p26 avrh g vss p57 p58 p59 p5a p5b vss vss pb7 pb6 pb5 pb4 pb3 avrl h p5c p5d p30 p31 p32 p33 vss vss p1f p1e pb2 pb1 pb0 avss j vss p37 p36 p35 p34 p70 vss p76 p1d p1c p1b p1a p19 avcc k p38 p39 p3a p3b p4a p4e vss p74 p7b p7f p18 p16 p15 p17 l p3c p3d p3e p43 p49 p4d vss p73 p7a p7e p14 p13 p12 vss m vss p3f p42 p44 p48 p4c vss p72 p79 pf0 pf2 p11 p10 vcc n vcc p40 p41 p45 initx p4b vss p71 p78 p7d pf1 md0 md1 vss p c vss vcc x0a x1a vss p75 p77 p7c vss x0 x1
document number: 002 - 05661 rev. *d page 12 of 131 mb9b520ta series 4. list of pin functions list of pin numbers the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pin s, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. pin no pin name i/o circuit type pin state type lqfp - 1 76 l qfp - 144 bga - 1 9 2 1 1 c1 vcc - 2 2 b2 pa0 i * j sin8_0 tioa08_0 mad21_0 3 3 c2 pa1 i* j sot8_0 tioa09_0 mad22_0 4 4 c3 pa2 i* j sck8_0 tioa10_0 mad23_0 5 5 d5 pa3 i* j sin9_0 tioa11_0 mad24_0 6 6 d2 pa4 i * k rx0_2 sot9_0 tioa12_0 int03_0 7 7 d1 pa5 i * k tx0_2 sck9_0 tioa13_0 int10_2 8 8 d3 p05 e q traced0 sin4_2 tioa05_2 int00_1 9 9 d4 p06 e q traced1 sot4_2 tiob05_2 int01_1 10 10 e2 p07 e p traced2 adtg_0 sck4_2
document number: 002 - 05661 rev. *d page 13 of 131 mb9b520ta series pin no pin name i/o circuit type pin state type lqfp - 176 lqfp - 144 bga - 192 11 11 e3 p08 e p traced3 cts4_2 tioa00_2 12 12 e4 p09 e p traceclk rts4_2 tiob00_2 13 13 e5 p50 e k sin3_1 ain0_2 int00_0 moex_0 14 14 f1 p51 e k sot3_1 bin0_2 int01_0 mwex_0 15 15 f2 p52 e k sck3_1 zin0_2 int02_0 mdqm0_0 16 16 f3 p53 e k sin6_0 tioa01_2 int07_2 mdqm1_0 17 17 f4 p54 e j sot6_0 tiob01_2 male_0 18 18 f5 p55 e j adtg_1 sck6_0 mrdy_0 19 19 f6 p56 i* s sin1_0 tioa09_2 int08_2 cec1_1 mnale_0
document number: 002 - 05661 rev. *d page 14 of 131 mb9b520ta series pin no pin name i/o circuit type pin state type lqfp - 176 lqfp - 144 bga - 192 20 20 g2 p57 i* k sot1_0 tiob09_2 int16_1 mncle_0 21 21 g3 p58 i* k sck1_0 tioa11_2 int17_1 mnwex_0 22 22 g4 p59 e k sin7_0 tiob11_2 int09_2 mnrex_0 23 23 g5 p5a e k sot7_0 tioa13_1 int18_1 mcsx0_0 24 24 g6 p5b e k sck7_0 tiob13_1 int19_1 mcsx1_0 25 - h1 p5c e k tioa06_2 int28_0 26 - h2 p5d e k tiob06_2 int29_0 27 25 a5 vss - 28 - h3 p30 e u ain0_0 tiob00_1 int03_2 wkup4 29 - h4 p31 e k sck6_1 bin0_0 tiob01_1 int04_2
document number: 002 - 05661 rev. *d page 15 of 131 mb9b520ta series pin no pin name i/o circuit type pin state type lqfp - 176 lqfp - 144 bga - 192 30 - h5 p32 e k sot6_1 zin0_0 tiob02_1 int05_2 31 - h6 p33 e k adtg_6 sin6_1 tiob03_1 int04_0 32 - j5 p34 e j tx0_1 frck0_0 tiob04_1 33 - j4 p35 e k rx0_1 ic03_0 tiob05_1 int08_1 34 26 j3 p36 e k sin5_2 ic02_0 tioa12_2 int09_1 35 27 j2 p37 e k sot5_2 ic01_0 tiob12_2 int10_1 36 28 k1 p38 e k sck5_2 ic00_0 int11_1 37 29 k2 p39 e j adtg_2 dtti0x_0 rtcco_2 subout_2 38 30 k3 p3a f j rto00_0 tioa00_1 39 31 k4 p3b f j rto01_0 tioa01_1
document number: 002 - 05661 rev. *d page 16 of 131 mb9b520ta series pin no pin name i/o circuit type pin state type lqfp - 176 lqfp - 144 bga - 192 40 32 l1 p3c f j rto02_0 tioa02_1 41 33 l2 p3d f j rto03_0 tioa03_1 42 34 l3 p3e f j rto04_0 tioa04_1 43 35 m2 p3f f j rto05_0 tioa05_1 44 36 a8 vss - 45 37 n1 vcc - 46 38 n2 p40 e k sin10_0 tioa00_0 int12_1 mcsx2_0 47 39 n3 p41 e k sot10_0 tioa01_0 int13_1 mcsx3_0 48 40 m3 p42 e j sck10_0 tioa02_0 mclkout_0 49 41 l4 p43 i * j adtg_7 sin11_0 tioa03_0 50 42 m4 p44 i * j sot11_0 tioa04_0 51 43 n4 p45 i * j sck11_0 tioa05_0 52 44 p2 c - 53 45 a11 vss - 54 46 p4 vcc - 55 47 p5 p46 d f x0a 56 48 p6 p47 d g x1a 57 49 n5 initx b c 58 50 m5 p48 e k sin3_2 int14_1
document number: 002 - 05661 rev. *d page 17 of 131 mb9b520ta series pin no pin name i/o circuit type pin state type lqfp - 1 76 l qfp - 144 bga - 1 9 2 59 51 l5 p49 e j sot3_2 ain0_1 tiob00_0 60 52 k5 p4a e j sck3_2 bin0_1 tiob01_0 madata00_0 61 53 n6 p4b e j igtrg0_0 zin0_1 tiob02_0 madata01_0 62 54 m6 p4c e j sck7_1 ain1_2 tiob03_0 madata02_0 63 55 l6 p4d e j sot7_1 bin1_2 tiob04_0 madata03_0 64 56 k6 p4e e k sin7_1 zin1_2 tiob05_0 int06_2 madata04_0 65 57 j6 p70 e j tx0_0 tioa04_2 madata05_0 66 58 n8 p71 e k rx0_0 tiob04_2 int13_2 madata06_0 67 59 m8 p72 e u sin2_0 int14_2 wkup2 madata07_0 68 60 l8 p73 e k sot2_0 int15_2 madata08_0
document number: 002 - 05661 rev. *d page 18 of 131 mb9b520ta series pin no pin name i/o circuit type pin state type lqfp - 1 76 l qfp - 144 bga - 1 9 2 69 61 k8 p74 e j sck2_0 madata09_0 70 62 p8 p75 e k adtg_8 sin3_0 int07_1 madata10_0 71 63 j8 p76 e k sot3_0 tioa07_2 int11_2 madata11_0 72 64 p9 p77 e k sck3_0 tiob07_2 int12_2 madata12_0 73 65 n9 p78 e j ain1_0 tioa15_0 madata13_0 74 66 m9 p79 e k bin1_0 tiob15_0 int23_1 madata14_0 - - m1 vss - - - p3 vss - 75 67 l9 p7a e k zin1_0 int24_1 madata15_0 76 - k9 p7b e k tiob07_0 int10_0 77 - p10 p7c e k tioa07_0 int11_0 78 - n10 p7d e k tioa14_1 int12_0 79 - l10 p7e e k tiob14_1 int24_0 80 - k10 p7f e k tioa15_1 int25_0
document number: 002 - 05661 rev. *d page 19 of 131 mb9b520ta series pin no pin name i/o circuit type pin state type lqfp - 1 76 l qfp - 144 bga - 1 9 2 81 - m10 pf0 i * s sin1_2 tiob15_1 int13_0 cec0_0 82 - n11 pf1 i * k sot1_2 tioa08_1 int14_0 83 - m11 pf2 i * k sck1_2 tiob08_1 int15_0 84 68 n13 pe0 c e md1 85 69 n12 md0 j d 86 70 p12 pe2 a a x0 87 71 p13 pe3 a b x1 88 72 e1 vss - 89 73 m14 vcc - - - p7 vss - - - n7 vss - 90 74 m13 p10 g l an00 91 75 m12 p11 g n an01 sin1_1 frck0_2 int02_1 wkup1 92 76 l13 p12 g l an02 sot1_1 ic00_2 93 77 l12 p13 g l an03 sck1_1 ic01_2 rtcco_1 subout_1 94 78 l11 p14 g m an04 sin0_1 ic02_2 int03_1 95 79 k13 p15 g l an05 sot0_1 ic03_2
document number: 002 - 05661 rev. *d page 20 of 131 mb9b520ta series pin no pin name i/o circuit type pin state type lqfp - 1 76 l qfp - 144 bga - 1 9 2 96 80 k12 p16 g m an06 sck0_1 int20_1 97 81 k14 p17 g m an07 sin2_2 int04_1 - - m7 vss - - - l7 vss - - - k7 vss - 98 82 k11 p18 g m an08 sot2_2 int21_1 99 83 j13 p19 g m an09 sck2_2 int22_1 100 84 j12 p1a g m an10 sin4_1 ic00_1 tioa13_2 int05_1 101 85 j11 p1b g m an11 sot4_1 ic01_1 tiob13_2 int25_1 102 86 j10 p1c g m an12 sck4_1 ic02_1 tioa14_2 int26_1 103 87 j9 p1d g m an13 cts4_1 ic03_1 tiob14_2 int27_1 104 88 h10 p1e g m an14 rts4_1 dtti0x_1 tioa15_2 int28_1
document number: 002 - 05661 rev. *d page 21 of 131 mb9b520ta series pin no pin name i/o circuit type pin state type lqfp - 1 76 l qfp - 144 bga - 1 9 2 105 89 h9 p1f g m an15 adtg_5 frck0_1 tiob15_2 int29_1 106 - h13 pb0 e k sin7_2 tioa09_1 int16_0 107 - h12 pb1 e k sot7_2 tiob09_1 int17_0 108 - h11 pb2 e k sck7_2 tioa10_1 int18_0 109 - g13 pb3 e k tiob10_1 int19_0 110 - g12 pb4 e k sin0_2 tioa11_1 int20_0 111 - g11 pb5 e k sot0_2 tiob11_1 int21_0 112 - g10 pb6 e k sck0_2 tioa12_1 int22_0 113 - g9 pb7 e k tiob12_1 int23_0 114 90 j14 avcc - 115 91 h14 avss - - - j7 vss - - - p11 vss - 116 92 g14 av rl - 117 93 f14 avrh - 118 94 f10 p29 g l an16 sin12_0 119 95 f11 p28 g m an17 adtg_4 sot12_0 rto05_1 int09_0
document number: 002 - 05661 rev. *d page 22 of 131 mb9b520ta series pin no pin name i/o circuit type pin state type lqfp - 1 76 l qfp - 144 bga - 1 9 2 120 96 f12 p27 g m an18 sck12_0 rto04_1 int02_2 121 97 f13 p26 g l an19 sck2_1 rto03_1 122 98 e10 p25 g l an20 sot2_1 rto02_1 123 99 e11 p24 g m an21 sin2_1 rto01_1 int01_2 124 100 e12 p23 g l an22 sck0_0 rto00_1 tioa07_1 125 101 e13 p22 g l an23 sot0_0 zin1_1 tiob07_1 126 102 d12 p21 e k sin0_0 bin1_1 int06_1 127 103 d13 p20 e k ain1_1 int05_0 crout _0 128 104 c13 pf6 i* h nmix wkup0 129 105 e14 p82 e j mcsx7_0 130 106 d14 p83 e j mcsx6_0 131 107 c14 vcc - 132 108 g7 vss - 133 109 a13 vcc - 134 110 b13 p00 e i trstx 135 111 a12 p01 e i tck swclk
document number: 002 - 05661 rev. *d page 23 of 131 mb9b520ta series pin no pin name i/o circuit type pin state type lqfp - 1 76 l qfp - 144 bga - 1 9 2 136 112 c12 p02 e i tdi 137 113 b12 p03 e i tms swdio 138 114 b11 p04 e i tdo swo 139 - c11 p90 e k tiob08_0 int30_0 - - n14 vss - 140 - d11 p91 e k tiob09_0 int31_0 141 - b10 p92 e j sin5_1 tiob10_0 142 - c10 p93 e j sot5_1 tiob11_0 143 - d10 p94 e k sck5_1 tiob12_0 int26_0 144 - b9 p95 e k tiob13_0 int27_0 145 115 c9 pc0 h o da0_0 sin13_0 mcsx5_0 146 116 b8 pc1 h o da1_0 sot13_0 mcsx4_0 147 117 d9 pc2 e j sck13_0 mad00_0 148 118 e9 pc3 e j tioa06_1 mad01_0 149 119 f9 pc4 i * r sin14_0 tioa08_2 cec0_1 mad02_0 150 120 c8 pc5 i * j sot14_0 tioa10_2 mad03_0 - - l14 vss -
document number: 002 - 05661 rev. *d page 24 of 131 mb9b520ta series pin no pin name i/o circuit type pin state type lqfp - 1 76 l qfp - 144 bga - 1 9 2 151 121 d8 pc6 i * j sck14_0 tioa14_0 mad04_0 152 122 e8 pc7 e j crout_1 rtcco_0 subout_0 mad05_0 153 123 a10 pc8 e j sin15_0 mad06_0 154 124 f8 pc9 e j sot15_0 mad07_0 155 125 b7 pca e j sck15_0 mad08_0 156 126 a9 vcc - 157 127 g8 vss - 158 128 a7 pcb e j mad09_0 159 129 c7 pcc e j mad10_0 160 130 a6 pcd e j mad11_0 161 131 d7 pce e j rts4_0 tiob06_1 mad12_0 162 132 e7 pcf e j cts4_0 tiob08_2 mad13_0 163 133 f7 pd0 e k sck4_0 tiob10_2 int30_1 mad14_0 164 134 b6 pd1 e k sot4_0 tiob14_0 int31_1 mad15_0 - - b14 vss - - - h7 vss - - - b1 vss - - - g1 vss -
document number: 002 - 05661 rev. *d page 25 of 131 mb9b520ta series pin no pin name i/o circuit type pin state type lqfp - 1 76 lqfp - 144 bga - 192 165 135 c6 pd2 e k sin4_0 tioa03_2 int00_2 mad16_0 166 136 d6 pd3 e j tiob03_2 mad17_0 167 137 e6 p62 e j adtg_3 sck5_0 mad18_0 168 138 b5 p61 e j uhconx sot5_0 tiob02_2 mad19_0 169 139 c5 p60 e u sin5_0 tioa02_2 int15_1 wkup5 mad20_0 170 - b4 pf3 i * k sin6_2 tioa06_0 int06_0 171 - c4 pf4 i * k sot6_2 tiob06_0 int07_0 172 140 b3 pf5 i * t igtrg0_1 int08_0 wkup3 cec1_0 - sck6_2 173 141 a4 usbvcc - 174 142 a3 p80 k v udm0 175 143 a2 p81 k v udp0 176 144 h8 vss - - - j1 vss - * : 5v tolerant i/o
document number: 002 - 05661 rev. *d page 26 of 131 mb9b520ta series list of pin functions the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pin s, there are multiple pins that provide the same function for the same channel. use the extended port function register ( epfr) to select the pin. pin function pin name function description pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 adc adtg_0 a/d converter external trigger input pin 10 10 e2 adtg_1 18 18 f5 adtg_2 37 29 k2 adtg_3 167 137 e6 adtg_4 119 95 f11 adtg_5 105 89 h9 adtg_6 31 - h6 adtg_7 49 41 l4 adtg_8 70 62 p8 an00 a/d converter analog input pin . anxx describes adc ch.xx . 90 74 m13 an01 91 75 m12 an02 92 76 l13 an03 93 77 l12 an04 94 78 l11 an05 95 79 k13 an06 96 80 k12 an07 97 81 k14 an08 98 82 k11 an09 99 83 j13 an10 100 84 j12 an11 101 85 j11 an12 102 86 j10 an13 103 87 j9 an14 104 88 h10 an15 105 89 h9 an16 118 94 f10 an17 119 95 f11 an18 120 96 f12 an19 121 97 f13 an20 122 98 e10 an21 123 99 e11 an22 124 100 e12 an23 125 101 e13 base timer 0 tioa 0 0_0 base timer ch.0 tioa pin 46 38 n2 tioa 0 0_1 38 30 k3 tioa 0 0_2 11 11 e3 tiob 0 0_0 base timer ch.0 tiob pin 59 51 l5 tiob 0 0_1 28 - h3 tiob 0 0_2 12 12 e4 base timer 1 tioa 0 1_0 base timer ch.1 tioa pin 47 39 n3 tioa 0 1_1 39 31 k4 tioa 0 1_2 16 16 f3 tiob 0 1_0 base timer ch.1 tiob pin 60 52 k5 tiob 0 1_1 29 - h4 tiob 0 1_2 17 17 f4 base timer 2 tioa 0 2_0 base timer ch.2 tioa pin 48 40 m3 tioa 0 2_1 40 32 l1 tioa 0 2_2 169 139 c5 tiob 0 2_0 base timer ch.2 tiob pin 61 53 n6 tiob 0 2_1 30 - h5 tiob 0 2_2 168 138 b5
document number: 002 - 05661 rev. *d page 27 of 131 mb9b520ta series pin function pin name function description pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 base timer 3 tioa 0 3_0 base timer ch.3 tioa pin 49 41 l4 tioa 0 3_1 41 33 l2 tioa 0 3_2 165 135 c6 tiob 0 3_0 base timer ch.3 tiob pin 62 54 m6 tiob 0 3_1 31 - h6 tiob 0 3_2 166 136 d6 base timer 4 tioa 0 4_0 base timer ch.4 tioa pin 50 42 m4 tioa 0 4_1 42 34 l3 tioa 0 4_2 65 57 j6 tiob 0 4_0 base timer ch.4 tiob pin 63 55 l6 tiob 0 4_1 32 - j5 tiob 0 4_2 66 58 n8 base timer 5 tioa 0 5_0 base timer ch.5 tioa pin 51 43 n4 tioa 0 5_1 43 35 m2 tioa 0 5_2 8 8 d3 tiob 0 5_0 base timer ch.5 tiob pin 64 56 k6 tiob 0 5_1 33 - j4 tiob 0 5_2 9 9 d4 base timer 6 tioa 0 6_ 0 base timer ch.6 tioa pin 170 - b4 tioa 0 6_1 148 118 e9 tioa 0 6_ 2 25 - h1 tiob 0 6_ 0 base timer ch.6 tiob pin 171 - c4 tiob 0 6_1 161 131 d7 tiob 0 6_ 2 26 - h2 base timer 7 tioa07_0 base timer ch.7 tioa pin 77 - p10 tioa07_1 124 100 e12 tioa07_2 71 63 j8 tiob07_0 base timer ch.7 tiob pin 76 - k9 tiob07_1 125 101 e13 tiob07_2 72 64 p9 base timer 8 tioa08_0 base timer ch.8 tioa pin 2 2 b2 tioa08_1 82 - n11 tioa08_2 149 119 f9 tiob08_0 base timer ch.8 tiob pin 139 - c11 tiob08_1 83 - m11 tiob08_2 162 132 e7 base timer 9 tioa09_0 base timer ch.9 tioa pin 3 3 c2 tioa09_1 106 - h13 tioa09_2 19 19 f6 tiob09_0 base timer ch.9 tiob pin 140 - d11 tiob09_1 107 - h12 tiob09_2 20 20 g2 base timer 10 tioa10_0 base timer ch.10 tioa pin 4 4 c3 tioa10_1 108 - h11 tioa10_2 150 120 c8 tiob10_0 base timer ch.10 tiob pin 141 - b10 tiob10_1 109 - g13 tiob10_2 163 133 f7 base timer 11 tioa11_0 base timer ch.11 tioa pin 5 5 d5 tioa11_1 110 - g12 tioa11_2 21 21 g3 tiob11_0 base timer ch.11 tiob pin 142 - c10 tiob11_1 111 - g11 tiob11_2 22 22 g4
document number: 002 - 05661 rev. *d page 28 of 131 mb9b520ta series pin function pin name function description pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 base timer 12 tioa12_0 base timer ch.12 tioa pin 6 6 d2 tioa12_1 112 - g10 tioa12_2 34 26 j3 tiob12_0 base timer ch.12 tiob pin 143 - d10 tiob12_1 113 - g9 tiob12_2 35 27 j2 base timer 13 tioa13_0 base timer ch.13 tioa pin 7 7 d1 tioa13_1 23 23 g5 tioa13_2 100 84 j12 tiob13_0 base timer ch.13 tiob pin 144 - b9 tiob13_1 24 24 g6 tiob13_2 101 85 j11 base timer 14 tioa14_0 base timer ch.14 tioa pin 151 121 d8 tioa14_1 78 - n10 tioa14_2 102 86 j10 tiob14_0 base timer ch.14 tiob pin 164 134 b6 tiob14_1 79 - l10 tiob14_2 103 87 j9 base timer 15 tioa15_0 base timer ch.15 tioa pin 73 65 n9 tioa15_1 80 - k10 tioa15_2 104 88 h10 tiob15_0 base timer ch.15 tiob pin 74 66 m9 tiob15_1 81 - m10 tiob15_2 105 89 h9 debugger swclk serial wire debug interface clock input 135 111 a12 swdio serial wire debug interface data input / output 137 113 b12 swo serial wire viewer output 138 114 b11 tck jtag test clock input 135 111 a12 tdi jtag test data input 136 112 c12 tdo jtag debug data output 138 114 b11 tms jtag test mode state input/output 137 113 b12 traceclk trace clk output of etm 12 12 e4 traced0 trace data output of etm 8 8 d3 traced1 9 9 d4 traced2 10 10 e2 traced3 11 11 e3 trstx jtag test reset input 134 110 b13
document number: 002 - 05661 rev. *d page 29 of 131 mb9b520ta series pin function pin name function description pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 external bus mad00 _0 external bus interface address bus 147 117 d9 mad01 _0 148 118 e9 mad02 _0 149 119 f9 mad03 _0 150 120 c8 mad04 _0 151 121 d8 mad05 _0 152 122 e8 mad06 _0 153 123 a10 mad07 _0 154 124 f8 mad08 _0 155 125 b7 mad09 _0 158 128 a7 mad10 _0 159 129 c7 mad11 _0 160 130 a6 mad12 _0 161 131 d7 mad13 _0 162 132 e7 mad14 _0 163 133 f7 mad15_0 164 134 b6 mad16 _0 165 135 c6 mad17 _0 166 136 d6 mad18 _0 167 137 e6 mad19 _0 168 138 b5 mad20 _0 169 139 c5 mad21 _0 2 2 b2 mad2 2_0 3 3 c2 mad23 _0 4 4 c3 mad24 _0 5 5 d5 mcsx0_0 external bus interface chip select output pin 23 23 g5 mcsx1_0 24 24 g6 mcsx2_0 46 38 n2 mcsx3_0 47 39 n3 mcsx4_0 146 116 b8 mcsx5_0 145 115 c9 mcsx6_0 130 106 d14 mcsx7_0 129 105 e14 mdqm0_0 external bus interface byte mask signal output 15 15 f2 mdqm1_0 16 16 f3 moex_0 external bus interface read enable signal for sram 13 13 e5 mwex_0 external bus interface write enable signal for sram 14 14 f1
document number: 002 - 05661 rev. *d page 30 of 131 mb9b520ta series pin function pin name function description pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 external bus mnale_0 external bus interface ale signal to control nand flash output pin 19 19 f6 mncle_0 external bus interface cle signal to control nand flash output pin 20 20 g2 mnrex_0 external bus interface read enable signal to control nand flash 22 22 g4 mnwex_0 external bus interface write enable signal to control nand flash 21 21 g3 m a data0 0_0 external bus interface data bus (address / data multiplex bus) 60 52 k5 m a data0 1_0 61 53 n6 m a data0 2_0 62 54 m6 m a data0 3_0 63 55 l6 m a data0 4_0 64 56 k6 m a data0 5_0 65 57 j6 m a data0 6_0 66 58 n8 m a data0 7_0 67 59 m8 m a data0 8_0 68 60 l8 m a data0 9_0 69 61 k8 m a data 10_0 70 62 p8 m a data 11_0 71 63 j8 m a data 12_0 72 64 p9 m a data 13_0 73 65 n9 m a data 14_0 74 66 m9 m a data 15_0 75 67 l9 male_0 external bus interface address latch enable output signal for multiplex 17 17 f4 mrdy_0 external bus interface external rdy input signal 18 18 f5 mclkout_0 external bus interface external clock output 48 40 m3
document number: 002 - 05661 rev. *d page 31 of 131 mb9b520ta series pin function pin name function description pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 external interrupt int00_0 external interrupt request 00 input pin 13 13 e5 int00_1 8 8 d3 int00_2 165 135 c6 int01_0 external interrupt request 01 input pin 14 14 f1 int01_1 9 9 d4 int01_2 123 99 e11 int02_0 external interrupt request 02 input pin 15 15 f2 int02_1 91 75 m12 int02_2 120 96 f12 int03_0 external interrupt request 03 input pin 6 6 d2 int03_1 94 78 l11 int03_2 28 - h3 int04_0 external interrupt request 04 input pin 31 - h6 int04_1 97 81 k14 int04_2 29 - h4 int05_0 external interrupt request 05 input pin 127 103 d13 int05_1 100 84 j12 int05_2 30 - h5 int06_0 external interrupt request 06 input pin 170 - b4 int06_1 126 102 d12 int06_2 64 56 k6 int07_0 external interrupt request 07 input pin 171 - c4 int07_1 70 62 p8 int07_2 16 16 f3 int08_0 external interrupt request 08 input pin 172 140 b3 int08_1 33 - j4 int08_2 19 19 f6 int09_0 external interrupt request 09 input pin 119 95 f11 int09_1 34 26 j3 int09_2 22 22 g4 int10_0 external interrupt request 10 input pin 76 - k9 int10_1 35 27 j2 int10_2 7 7 d1 int11_0 external interrupt request 11 input pin 77 - p10 int11_1 36 28 k1 int11_2 71 63 j8 int12_0 external interrupt request 12 input pin 78 - n10 int12_1 46 38 n2 int12_2 72 64 p9 int13_0 external interrupt request 13 input pin 81 - m10 int13_1 47 39 n3 int13_2 66 58 n8 int14_0 external interrupt request 14 input pin 82 - n11 int14_1 58 50 m5 int14_2 67 59 m8
document number: 002 - 05661 rev. *d page 32 of 131 mb9b520ta series pin function pin name function description pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 external interrupt int15_0 external interrupt request 15 input pin 83 - m11 int15_1 169 139 c5 int15_2 68 60 l8 int16_0 external interrupt request 16 input pin 106 - h13 int16_1 20 20 g2 int17_0 external interrupt request 17 input pin 107 - h12 int17_1 21 21 g3 int18_0 external interrupt request 18 input pin 108 - h11 int18_1 23 23 g5 int19_0 external interrupt request 19 input pin 109 - g13 int19_1 24 24 g6 int20_0 external interrupt request 20 input pin 110 - g12 int20_1 96 80 k12 int21_0 external interrupt request 21 input pin 111 - g11 int21_1 98 82 k11 int22_0 external interrupt request 22 input pin 112 - g10 int22_1 99 83 j13 int23_0 external interrupt request 23 input pin 113 - g9 int23_1 74 66 m9 int24_0 external interrupt request 24 input pin 79 - l10 int24_1 75 67 l9 int25_0 external interrupt request 25 input pin 80 - k10 int25_1 101 85 j11 int26_0 external interrupt request 26 input pin 143 - d10 int26_1 102 86 j10 int27_0 external interrupt request 27 input pin 144 - b9 int27_1 103 87 j9 int28_0 external interrupt request 28 input pin 25 - h1 int28_1 104 88 h10 int29_0 external interrupt request 29 input pin 26 - h2 int29_1 105 89 h9 int30_0 external interrupt request 30 input pin 139 - c11 int30_1 163 133 f7 int31_0 external interrupt request 31 input pin 140 - d11 int31_1 164 134 b6 nmix non - maskable interrupt input 128 104 c13
document number: 002 - 05661 rev. *d page 33 of 131 mb9b520ta series pin function pin name function description pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 gpio p00 general - purpose i/o port 0 134 110 b13 p01 135 111 a12 p02 136 112 c12 p03 137 113 b12 p04 138 114 b11 p05 8 8 d3 p06 9 9 d4 p07 10 10 e2 p08 11 11 e3 p09 12 12 e4 p10 general - purpose i/o port 1 90 74 m13 p11 91 75 m12 p12 92 76 l13 p13 93 77 l12 p14 94 78 l11 p15 95 79 k13 p16 96 80 k12 p17 97 81 k14 p18 98 82 k11 p19 99 83 j13 p1a 100 84 j12 p1b 101 85 j11 p1c 102 86 j10 p1d 103 87 j9 p1e 104 88 h10 p1f 105 89 h9 p20 general - purpose i/o port 2 127 103 d13 p21 126 102 d12 p22 125 101 e13 p2 3 124 100 e12 p2 4 123 99 e11 p2 5 122 98 e10 p2 6 121 97 f13 p2 7 120 96 f12 p2 8 119 95 f11 p2 9 118 94 f10
document number: 002 - 05661 rev. *d page 34 of 131 mb9b520ta series pin function pin name function description pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 gpio p30 general - purpose i/o port 3 28 - h3 p31 29 - h4 p32 30 - h5 p33 31 - h6 p34 32 - j5 p35 33 - j4 p36 34 26 j3 p37 35 27 j2 p38 36 28 k1 p39 37 29 k2 p3a 38 30 k3 p3b 39 31 k4 p3c 40 32 l1 p3d 41 33 l2 p3e 42 34 l3 p3f 43 35 m2 p40 general - purpose i/o port 4 46 38 n2 p41 47 39 n3 p42 48 40 m3 p43 49 41 l4 p44 50 42 m4 p45 51 43 n4 p46 55 47 p5 p47 56 48 p6 p48 58 50 m5 p49 59 51 l5 p4a 60 52 k5 p4b 61 53 n6 p4c 62 54 m6 p4d 63 55 l6 p4e 64 56 k6 p50 general - purpose i/o port 5 13 13 e5 p51 14 14 f1 p52 15 15 f2 p53 16 16 f3 p54 17 17 f4 p55 18 18 f5 p56 19 19 f6 p57 20 20 g2 p58 21 21 g3 p59 22 22 g4 p5a 23 23 g5 p5b 24 24 g6 p5c 25 - h1 p5 d 26 - h2
document number: 002 - 05661 rev. *d page 35 of 131 mb9b520ta series pin function pin name f unction description pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 gpio p60 general - purpose i/o port 6 169 139 c5 p61 168 138 b5 p62 167 137 e6 p 7 0 general - purpose i/o port 7 65 57 j6 p 7 1 66 58 n8 p 7 2 67 59 m8 p 7 3 68 60 l8 p 7 4 69 61 k8 p 7 5 70 62 p8 p 7 6 71 63 j8 p 7 7 72 64 p9 p 7 8 73 65 n9 p 7 9 74 66 m9 p 7 a 75 67 l9 p 7 b 76 - k9 p 7 c 77 - p10 p 7 d 78 - n10 p 7 e 79 - l10 p 7 f 80 - k10 p80 general - purpose i/o port 8 174 142 a3 p81 175 143 a2 p82 129 105 e14 p83 130 106 d14 p90 general - purpose i/o port 9 139 - c11 p91 140 - d11 p92 141 - b10 p93 142 - c10 p94 143 - d10 p95 144 - b9 pa0 general - purpose i/o port a 2 2 b2 pa1 3 3 c2 pa2 4 4 c3 pa3 5 5 d5 pa4 6 6 d2 pa5 7 7 d1 pb0 general - purpose i/o port b 106 - h13 pb1 107 - h12 pb2 108 - h11 pb3 109 - g13 pb4 110 - g12 pb5 111 - g11 pb6 112 - g10 pb7 113 - g9
document number: 002 - 05661 rev. *d page 36 of 131 mb9b520ta series pin function pin name function description pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 gpio pc0 general - purpose i/o port c 145 115 c9 pc1 146 116 b8 pc2 147 117 d9 pc3 148 118 e9 pc4 149 119 f9 pc5 150 120 c8 pc6 151 121 d8 pc7 152 122 e8 pc8 153 123 a10 pc9 154 124 f8 pca 155 125 b7 pcb 158 128 a7 pcc 159 129 c7 pcd 160 130 a6 pce 161 131 d7 pcf 162 132 e7 pd0 general - purpose i/o port d 163 133 f7 pd1 164 134 b6 pd2 165 135 c6 pd3 166 136 d6 pe0 general - purpose i/o port e 84 68 n13 pe2 86 70 p12 pe3 87 71 p13 pf0 general - purpose i/o port f * 81 - m10 pf1 82 - n11 pf2 83 - m11 pf3 170 - b4 pf4 171 - c4 pf5 172 140 b3 pf6 128 104 c13 multi function serial 0 sin0_0 multifunction serial interface ch.0 input pin 126 102 d12 sin0_1 94 78 l11 sin0_ 2 110 - g12 sot0_0 (sda0_0) multifunction serial interface ch.0 output pin. this pin operates as sot0 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda0 when it is used in an i 2 c (operation mode 4). 125 101 e13 sot0_1 (sda0_1) 95 79 k13 sot0_ 2 (sda0_ 2 ) 111 - g11 sck0_0 (scl0_0) multifunction serial interface ch.0 clock i/o pin. this pin operates as sck0 when it is used in a uart/csio (operation modes 0 to 2) and as scl0 when it is used in an i 2 c (operation mode 4). 124 100 e12 sck0_ 1 (scl0_ 1 ) 96 80 k12 sck0_ 2 (scl0_ 2 ) 112 - g10
document number: 002 - 05661 rev. *d page 37 of 131 mb9b520ta series pin function pin name function description pin no. lqfp - 1 76 l qfp - 1 44 bga - 1 92 multi function serial 1 sin1_ 0 multifunction serial interface ch.1 input pin 19 19 f6 sin1_1 91 75 m12 sin1_ 2 81 - m10 sot1_ 0 (sda1_ 0 ) multifunction serial interface ch.1 output pin. this pin operates as sot1 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda1 when it is used in an i 2 c (operation mode 4). 20 20 g2 sot1_1 (sda1_1) 92 76 l13 sot1_ 2 (sda1_ 2 ) 82 - n11 sck1_ 0 (scl1_ 0 ) multifunction serial interface ch.1 clock i/o pin. this pin operates as sck1 when it is used in a uart/csio (operation modes 0 to 2) and as scl1 when it is used in an i 2 c (operation mode 4). 21 21 g3 sck1_1 (scl1_1) 93 77 l12 sck1_ 2 (scl1_ 2 ) 83 - m11 multi function serial 2 sin2_ 0 multifunction serial interface ch.2 input pin 67 59 m8 sin2_ 1 123 99 e11 sin2_ 2 97 81 k14 sot2_ 0 (sda2_ 0 ) multifunction serial interface ch.2 output pin. this pin operates as sot2 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda2 when it is used in an i 2 c (operation mode 4). 68 60 l8 sot2_ 1 (sda2_ 1 ) 122 98 e10 sot2_ 2 (sda2_ 2 ) 98 82 k11 sck2_ 0 (scl2_ 0 ) multifunction serial interface ch.2 clock i/o pin. this pin operates as sck2 when it is used in a uart/csio (operation modes 0 to 2) and as scl2 when it is used in an i 2 c (operation mode 4). 69 61 k8 sck2_ 1 (scl2_ 1 ) 121 97 f13 sck2_ 2 (scl2_ 2 ) 99 83 j13 multi function serial 3 sin3_ 0 multifunction serial interface ch.3 input pin 70 62 p8 sin3_ 1 13 13 e5 sin3_ 2 58 50 m5 sot3_ 0 (sda3_ 0 ) multifunction serial interface ch.3 output pin. this pin operates as sot3 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda3 when it is used in an i 2 c (operation mode 4). 71 63 j8 sot3_ 1 (sda3_ 1 ) 14 14 f1 sot3_ 2 (sda3_ 2 ) 59 51 l5 sck3_ 0 (scl3_ 0 ) multifunction serial interface ch.3 clock i/o pin. this pin operates as sck3 when it is used in a uart/csio (operation modes 0 to 2) and as scl3 when it is used in an i 2 c (operation mode 4). 72 64 p9 sck3_ 1 (scl3_ 1 ) 15 15 f2 sck3_ 2 (scl3_ 2 ) 60 52 k5
document number: 002 - 05661 rev. *d page 38 of 131 mb9b520ta series pin function pin name function description pin no. lqfp - 1 76 l qfp - 1 44 bga - 1 92 multi function serial 4 sin4_0 multifunction serial interface ch.4 input pin 165 135 c6 sin4_1 100 84 j12 sin4_2 8 8 d3 sot4_0 (sda4_0) multifunction serial interface ch.4 output pin. this pin operates as sot4 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda4 when it is used in an i 2 c (operation mode 4). 164 134 b6 sot4_1 (sda4_1) 101 85 j11 sot4_2 (sda4_2) 9 9 d4 sck4_0 (scl4_0) multifunction serial interface ch.4 clock i/o pin. this pin operates as sck4 when it is used in a uart/csio (operation modes 0 to 2) and as scl4 when it is used in an i 2 c (operation mode 4). 163 133 f7 sck4_1 (scl4_1) 102 86 j10 sck4_2 (scl4_2) 10 10 e2 rts4_0 multifunction serial interface ch.4 rts output pin 161 131 d7 rts4_1 104 88 h10 rts4_2 12 12 e4 cts4_0 multifunction serial interface ch.4 cts input pin 162 132 e7 cts4_1 103 87 j9 cts4_2 11 11 e3 multi function serial 5 sin5_0 multifunction serial interface ch.5 input pin 169 139 c5 sin5_ 1 141 - b10 sin5_2 34 26 j3 sot5_0 (sda5_0) multifunction serial interface ch.5 output pin. this pin operates as sot5 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda5 when it is used in an i 2 c (operation mode 4). 168 138 b5 sot5_ 1 (sda5_ 1 ) 142 - c10 sot5_2 (sda5_2) 35 27 j2 sck5_0 (scl5_0) multifunction serial interface ch.5 clock i/o pin. this pin operates as sck5 when it is used in a uart/csio (operation modes 0 to 2) and as scl5 when it is used in an i 2 c (operation mode 4). 167 137 e6 sck5_ 1 (scl5_ 1 ) 143 - d10 sck5_2 (scl5_2) 36 28 k1 multi function serial 6 sin6_0 multifunction serial interface ch.6 input pin 16 16 f3 sin6_1 31 - h6 sin6_ 2 170 - b4 sot6_0 (sda6_0) multifunction serial interface ch.6 output pin. this pin operates as sot6 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda6 when it is used in an i 2 c (operation mode 4). 17 17 f4 sot6_1 (sda6_1) 30 - h5 sot6_ 2 (sda6_ 2 ) 171 - c4 sck6_0 (scl6_0) multifunction serial interface ch.6 clock i/o pin. this pin operates as sck6 when it is used in a uart/csio (operation modes 0 to 2) and as scl6 when it is used in an i 2 c (operation mode 4). 18 18 f5 sck6_1 (scl6_1) 29 - h4 sck6_ 2 (scl6_ 2 ) 172 - b3
document number: 002 - 05661 rev. *d page 39 of 131 mb9b520ta series pin function pin name function description pin no. lqfp - 1 76 l qfp - 1 44 bga - 1 92 multi function serial 7 sin7_ 0 multifunction serial interface ch.7 input pin 22 22 g4 sin7_ 1 64 56 k6 sin7_ 2 106 - h13 sot7_ 0 (sda7_ 0 ) multifunction serial interface ch.7 output pin. this pin operates as sot7 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda7 when it is used in an i 2 c (operation mode 4). 23 23 g5 sot7_ 1 (sda7_ 1 ) 63 55 l6 sot7_ 2 (sda7_ 2 ) 107 - h12 sck7_ 0 (scl7_ 0 ) multifunction serial interface ch.7 clock i/o pin. this pin operates as sck7 when it is used in a uart/csio (operation modes 0 to 2) and as scl7 when it is used in an i 2 c (operation mode 4). 24 24 g6 sck7_ 1 (scl7_ 1 ) 62 54 m6 sck7_ 2 (scl7_ 2 ) 108 - h11 multi function serial 8 sin 8 _0 mult ifunction serial interface ch. 8 input pin 2 2 b2 sot 8 _0 (sda 8 _0) multifunction serial interface ch.6 output pin. this pin operates as sot 8 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda 8 when it is used in an i 2 c (operation mode 4). 3 3 c2 sck 8 _0 (scl 8 _0) multifunction serial interface ch.7 clock i/o pin. this pin operates as sck 8 when it is used in a uart/csio (operation modes 0 to 2) and as scl 8 when it is used in an i 2 c (operation mode 4). 4 4 c3 multi function serial 9 sin 9 _ 0 mult ifunction serial interface ch. 9 input pin 5 5 d5 sot 9 _ 0 (sda 9 _ 0 ) mul tifunction serial interface ch. 9 output pin. this pin operates as sot 9 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda 9 when it is used in an i 2 c (operation mode 4). 6 6 d2 sck 9 _ 0 (scl 9 _ 0 ) multifunction serial interface ch. 9 clock i/o pin. this pin operates as sck 9 when it is used in a uart/csio (operation modes 0 to 2) and as scl 9 when it is used in an i 2 c (operation mode 4). 7 7 d1 multi function serial 10 sin 10 _0 mult ifunction serial interface ch. 10 input pin 46 38 n2 sot 10 _0 (sda 10 _0) mul tifunction serial interface ch. 10 output pin. this pin operates as sot 10 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda 10 when it is used in an i 2 c (operation mode 4). 47 39 n3 sck 10 _0 (scl 10 _0) multifunction serial interface ch. 10 clock i/o pin. this pin operates as sck 10 when it is used in a uart/csio (operation modes 0 to 2) and as scl 10 when it is used in an i 2 c (operation mode 4). 48 40 m3
document number: 002 - 05661 rev. *d page 40 of 131 mb9b520ta series pin function pin name function description pin no. lqfp - 1 76 l qfp - 1 44 bga - 1 92 multi function serial 11 sin 11 _ 0 mult ifunction serial interface ch. 11 input pin 49 41 l4 sot 11 _ 0 (sda 11 _ 0 ) mul tifunction serial interface ch. 11 output pin. this pin operates as sot 11 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda 11 when it is used in an i 2 c (operation mode 4). 50 42 m4 sck 11 _ 0 (scl 11 _ 0 ) multifunction serial interface ch. 11 clock i/o pin. this pin operates as sck 11 when it is used in a uart/csio (operation modes 0 to 2) and as scl 11 when it is used in an i 2 c (operation mode 4). 51 43 n4 multi function serial 12 sin 12 _0 mult ifunction serial interface ch. 12 input pin 118 94 f10 sot 12 _0 (sda 12 _0) mul tifunction serial interface ch. 12 output pin. this pin operates as sot 12 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda 12 when it is used in an i 2 c (operation mode 4). 119 95 f11 sck 12 _0 (scl 12 _0) multifunction serial interface ch. 12 clock i/o pin. this pin operates as sck 12 when it is used in a uart/csio (operation modes 0 to 2) and as scl 12 when it is used in an i 2 c (operation mode 4). 120 96 f12 multi function serial 13 sin 13 _ 0 mult ifunction serial interface ch. 13 input pin 145 115 c9 sot 13 _ 0 (sda 13 _ 0 ) mul tifunction serial interface ch. 13 output pin. this pin operates as sot 13 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda 13 when it is used in an i 2 c (operation mode 4). 146 116 b8 sck 13 _ 0 (scl 13 _ 0 ) multifunction serial interface ch. 13 clock i/o pin. this pin operates as sck 13 when it is used in a uart/csio (operation modes 0 to 2) and as scl 13 when it is used in an i 2 c (operation mode 4). 147 117 d9 multi function serial 14 sin 14 _0 multifunction serial interface ch. 14 input pin 149 119 f9 sot 14 _0 (sda 14 _0) multifunction serial interface ch. 14 output pin. this pin operates as sot 14 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda 14 when it is used in an i 2 c (operation mode 4). 150 120 c8 sck 14 _0 (scl 14 _0) multifunction serial interface ch. 14 clock i/o pin. this pin operates as sck 14 when it is used in a uart/csio (operation modes 0 to 2) and as scl 14 when it is used in an i 2 c (operation mode 4). 151 121 d8 multi function serial 15 sin 15 _ 0 multifunction se rial interface ch. 15 input pin 153 123 a10 sot 15 _ 0 (sda 15 _ 0 ) multifunction serial interface ch. 15 output pin. this pin operates as sot 15 when it is used in a uart/csio /lin (operation modes 0 to 3 ) and as sda 15 when it is used in an i 2 c (operation mode 4). 154 124 f8 sck 15 _ 0 (scl 15 _ 0 ) multifunction serial interface ch. 15 clock i/o pin. this pin operates as sck 15 when it is used in a uart/csio (operation modes 0 to 2) and as scl 15 when it is used in an i 2 c (operation mode 4). 155 125 b7
document number: 002 - 05661 rev. *d page 41 of 131 mb9b520ta series pin function pin name function description pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 multi function timer 0 dtti0x_0 input signal controlling wave form generator outputs rto00 to rto05 of multi - function timer 0. 37 29 k2 dtti0x_1 104 88 h10 frck0_0 16 - bit free - run timer ch.0 external clock input pin 32 - j5 frck0_1 105 89 h9 frck0_ 2 91 75 m12 ic00_0 16 - bit input capture ch.0 input pin of multi - function timer 0 . icxx describes chan n el number. 36 28 k1 ic00_1 100 84 j12 ic00_ 2 92 76 l13 ic01_0 35 27 j2 ic01_1 101 85 j11 ic01_ 2 93 77 l12 ic02_0 34 26 j3 ic02_1 102 86 j10 ic02_ 2 94 78 l11 ic03_0 33 - j4 ic03_1 103 87 j9 ic03_ 2 95 79 k13 rto00_0 (ppg00_0) wave form generator output of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg0 output modes. 38 30 k3 rto00_1 (ppg00_1) 124 100 e12 rto01_0 (ppg00_0) wave form generator output of multi - function timer 0 . this pin operates as ppg00 when it is used in ppg0 output modes. 39 31 k4 rto01_ 1 (ppg00_1) 123 99 e11 rto02_0 (ppg02_0) wave form generator output of multi - function timer 0 . this pin operates as ppg02 when it is used in ppg0 output modes. 40 32 l1 rto02_ 1 (ppg02_1) 122 98 e10 rto03_0 (ppg02_0) wave form generator output of multi - function timer 0 . this pin operates as ppg02 when it is used in ppg0 output modes. 41 33 l2 rto03_ 1 (ppg02_1) 121 97 f13 rto04_0 (ppg04_0) wave form generator output of multi - function timer 0 . this pin operates as ppg04 when it is used in ppg0 output modes. 42 34 l3 rto04_ 1 (ppg04_1) 120 96 f12 rto05_0 (ppg04_0) wave form generator output of multi - function timer 0 . this pin operates as ppg04 when it is used in ppg0 output modes. 43 35 m2 rto05_ 1 (ppg04_1) 119 95 f11 igtrg0_0 ppg igbt mode external trigger input pin 61 53 n6 igtrg0_1 172 140 b3
document number: 002 - 05661 rev. *d page 42 of 131 mb9b520ta series pin function pin name function description pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 quadrature position/ revolution counter 0 ain0_0 qprc ch.0 ain input pin 28 - h3 ain0_1 59 51 l5 ain0_2 13 13 e5 bin0_0 qprc ch.0 bin input pin 29 - h4 bin0_1 60 52 k5 bin0_2 14 14 f1 zin0_0 qprc ch.0 zin input pin 30 - h5 zin0_1 61 53 n6 zin0_2 15 15 f2 quadrature position/ revolution counter 1 ain1_0 qprc ch.1 ain input pin 73 65 n9 ain1_1 127 103 d13 ain1_2 62 54 m6 bin1_0 qprc ch.1 bin input pin 74 66 m9 bin1_1 126 102 d12 bin1_2 63 55 l6 zin1_0 qprc ch.1 zin input pin 75 67 l9 zin1_1 125 101 e13 zin1_2 64 56 k6 usb udm0 usb ch.0 device /host d C pin 174 142 a3 udp0 usb ch.0 device /host d + pin 175 143 a2 uhconx usb ch.0 usb external pull - up control pin 168 138 b5 can tx0_0 can interface ch.0 tx output 65 57 j6 tx0_1 32 - j5 tx0_2 7 7 d1 rx0_0 can interface ch.0 rx output 66 58 n8 rx0_1 33 - j4 rx0_2 6 6 d2 real - time clock rtcco_0 0.5 seconds pulse output pin of real - time clock 152 122 e8 rtcco_1 93 77 l12 rtcco_2 37 29 k2 subout_0 sub clock output pin 152 122 e8 subout_1 93 77 l12 subout_2 37 29 k2
document number: 002 - 05661 rev. *d page 43 of 131 mb9b520ta series pin function pin name function description pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 r eset initx external reset input. a reset is valid when initx="l". 57 49 n5 mode md0 mode 0 p in. during normal operation, md0="l" must be input. during serial programming to f lash memory, md0="h" must be input. 85 69 n12 md1 mode 1 p in. during serial programming to f lash memory, md1="l" must be input. 84 68 n13 p ower vcc power supply pin 1 1 c1 45 37 n1 54 46 p4 89 73 m14 131 107 c14 133 109 a13 156 126 a9 usbvcc 3.3v power supply port for usb i/o 173 141 a4 low - power consumption mode wkup0 deep standby mode return signal input pin 0 128 104 c13 wkup1 deep standby mode return signal input pin 1 91 75 m12 wkup2 deep standby mode return signal input pin 2 67 59 m8 wkup3 deep standby mode return signal input pin 3 172 140 b3 wkup4 deep standby mode return signal input pin 4 28 - h3 wkup5 deep standby mode return signal input pin 5 169 139 c5 hdmi - cec/ remote control reception cec0 _0 hdmi - cec/remote control reception ch.0 input/output pin 81 - m10 cec0_1 149 119 f9 cec1_0 hdmi - cec/remote control reception ch.1 input/output pin 172 140 b3 cec1 _1 19 19 f6 dac da0_0 d/a converter ch.0 analog output pin 145 115 c9 da1_0 d/a converter ch.1 analog output pin 146 116 b8
document number: 002 - 05661 rev. *d page 44 of 131 mb9b520ta series pin function pin name function description pin no lqfp - 1 76 l qfp - 1 44 bga - 1 92 gnd vss gnd pin 27 25 a5 44 36 a8 53 45 a11 88 72 e1 132 108 g7 157 127 g8 176 144 h8 - - m1 - - p3 - - p7 - - n7 - - m7 - - l7 - - k7 - - j7 - - p11 - - n14 - - l14 - - b14 - - h7 - - b1 - - g1 - - j1 c lock x0 main clock (oscillation) input pin 86 70 p12 x0a sub clock (oscillation) input pin 55 47 p5 x1 main clock (oscillation) i/o pin 87 71 p13 x1a sub clock (oscillation) i/o pin 56 48 p6 crout _0 built - in high - speed cr - osc clock output port 127 103 d13 crout _1 152 122 e8 analog p ower avcc a/d converter , d/a converter analog power pin 114 90 j14 avrh a/d converter analog reference voltage input pin 117 93 f14 analog gnd avss a/d converter , d/a converter gnd pin 115 91 h14 avrl a/d converter analog reference voltage input pin 116 92 g14 c pin c power supply stabilization capacity pin 52 44 p2 * : 5v tolerant i/o note: ? while this device contains a test access port (tap) based on the ieee 1149.1 - 2001 jtag standard, it is not fully compliant to all requirements of that standard. this device may contain a 32 - bit device id that is the same as the 32 - bit device id in other devices with different functionality. the tap pins may also be configurable for purposes other than access to the tap controller.
document number: 002 - 05661 rev. *d page 45 of 131 mb9b520ta series 5. i/o circuit type type circuit remarks a it is possible to select the main oscillation / gpio function when the main oscillation is selected. ? oscillation feedback resistor : approximately 1 m ? with standby mode control when the gpio is selected. ? cmos level o utput. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma b ? cmos level hysteresis input ? pull - up resistor : approximately 50 k p - ch p - ch n - ch r r p - ch p - ch n - ch x0 x1 pull - up resistor feedback resistor pull - up resistor pull - up resistor digital in put digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control
document number: 002 - 05661 rev. *d page 46 of 131 mb9b520ta series type circuit remarks c ? open drain output ? cmos level hysteresis input d it is possible to select the sub oscillation / gpio function when the sub oscillation is selected. ? oscillation feedback resistor : approximately 5 m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma p - ch p - ch n - ch r r p - ch p - ch n - ch x0 a x1 a pull - up resistor feedback resistor pull - up resistor digital input digital out put digital output digital output pull - up resistor control digital input standby mode control clock input standby mode control digital input standby mode control digital output digital output pull - up resistor control n-ch
document number: 002 - 05661 rev. *d page 47 of 131 mb9b520ta series type circuit remarks e ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off ? +b input available f ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 12 ma, i ol = 12 ma ? +b input available digital output digital output pull - up resistor control digital input standby mode c ontrol digital output digital output pull - up resistor control digital input standby mode c ontrol p-ch p-ch n-ch r
document number: 002 - 05661 rev. *d page 48 of 131 mb9b520ta series type circuit remarks g ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? when this pin is used as an i 2 c pin, the digital output p - ch transistor is always off ? +b input available h ? cmos level output ? cmos level hysteresis input ? with input control ? analog output ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma digital output digital output pull - up resistor control digital input standby mode c ontrol analog input input control p - c h p - c h n - c h a n a l o g o u t p u t r d i g i t a l o u t p u t d i g i t a l o u t p u t d i g i t a l i n p u t s t a n d b y m o d e c o n t r o l p u l l - u p r e s i s t o r c o n t r o l p-ch p-ch n-ch r
document number: 002 - 05661 rev. *d page 49 of 131 mb9b520ta series type circuit remarks i ? cmos level output ? cmos level hysteresis input ? 5v tolerant ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50 k ? i oh = - 4 ma, i ol = 4 ma ? available to control pzr registers. ? when this pin is used as an i 2 c pin, the digital outpu t p - ch transistor is always off j cmos level hysteresis input k it is possible to select the usb i/o / gpio function. when the usb i/o is selected. ? full - speed, low - speed control when the gpio is selected. ? cmos level output ? cmos level hysteresis input ? with standby mode control gpio digital output gpio digital input/output direction gpio digital input gpio digital input circuit control udp output usb full - speed/low - speed control udp input differential input usb/gpio select udm input udm output usb digital input/output direction gpio digital out put gpio digital input/output direction gpio digital input gpio digital input circuit control digital output digital output pull - up resistor control digital input standby mode c ontrol mode input p-ch p-ch n-ch r udp0/p81 udm0/p80 di f ferential
document number: 002 - 05661 rev. *d page 50 of 131 mb9b520ta series 6. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observ ed to minimi ze the chance of failure and to obtain higher reliability from your cypress semiconductor devices. 6.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. recommended operating conditions recommen ded operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. op eration outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the l isted conditions are advised to contact their sales representative beforehand. processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/outpu t functions. 1. preve nting over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the dev ice, and in extreme cases leads to permanent damage of the device. try to prevent su ch overvoltage or over - current conditions at the design stage. 2. protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows . such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. 3. handling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins should be connected through an appr opriate resistance to a power supply pin or ground pin. latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyrist or structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up. caution: the occurrence of latch - up not only causes loss of reliability in the semic onductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: 1. be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal no ise, surge levels, etc. 2. be sure that abnormal current flows do not occur during the power - on sequence. observance of safety regulations and standards most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. fail - safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, dam age or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions.
document number: 002 - 05661 rev. *d page 51 of 131 mb9b520ta series precautions related to usage of de vices cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers cons idering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (s uch as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. the company will not be responsible for damages arising from such use with out prior approval. 6.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during solderin g, you should only mount under cypress recommended conditions. for detailed information about mount conditions, contact your sales representative. lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the boar d, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in this case, the soldering process usually causes leads to be s ubjected t o thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfac es can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic lead s be verified before mounting. surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connec tions caused by deformed pins, or shorting due to solder bri dges. you must use appropriate mounting techniques. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordance with cypress ranking of recommended co nditions . lead - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduced under some conditions of use. storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reduci ng moisture resistan ce and causing packages to crack. to prevent, do the following: 1. avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. 2. use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 c and 30 c . when you open dry package that recommends humidity 40% to 70% relative humidity. 3. when necessary, cypress packages semicond uctor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. 4. avoid storing packages where they are exposed to corrosive gases or high levels of dust. b aking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the cypress recommended conditions for baking. condition: 125 c /24 h
document number: 002 - 05661 rev. *d page 52 of 131 mb9b520ta series static electricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. 2. electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. ground all fixtures and instruments, or protect with anti - static measures. 5. avoid the use of styrofoam or other highly static - prone materials for storage of completed board assemblies. 6.3 precaut ions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: 1. humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. 2. discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. 3. corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. radiation, including cosmic radiation most devices are not designed for environments involving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. 5. smok e, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in ot her special environmental conditions should consult with sales representatives.
document number: 002 - 05661 rev. *d page 53 of 131 mb9b520ta series 7. handling devices power supply pins in products with multiple v cc and v ss pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch - up. however, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operation of strobe signals caused by the rise in the groun d level, and to conform to the total output current rating. moreover, connect the current supply source with each power supply pin and gnd pin of this device at low impedance. it is also advisable that a ceramic capacitor of approximately 0.1 f be connect ed as a bypass capacitor between each power supply pin and gnd pin near this device. stabilizing power supply voltage a malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the recommende d operating c onditions of the vcc power supply voltage. as a rule, with voltage stabilization, suppress the voltage fluctuation so that the fluctuation in vcc ripple ( peak - to - peak value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the vcc value in the recommended operating conditions, and the transient fluctuation rate does not exceed 0.1 v/s when there is a momentary fluctuation on switching the power supply. crystal oscillator circuit noise near the x0 /x1 and x0a/ x1 a pins may cause the device to malfunction. design the printed circuit board so that x0 / x1, x0a/x1a pins, the crystal oscillator, and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended that the pc board artwork be designed such that the x0 /x1 and x0a/ x1 a pins are surrounded by ground plane as this is expected to produce stable operation. evaluate oscillation of your using crystal oscillator by your mount board. sub crystal oscillator this series sub oscillator circuit is low gain to keep the low current consumption. the crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillation. ? surface mount type size: more than 3.2 mm 1.5 mm load capacitance: approximately 6 pf to 7 pf ? lead type load capacitance: approximately 6 pf to 7 pf using an external clock when using an external cloc k as an input of the main clock , set x0 / x1 to the external clock input, and input the clock to x0 . x1 (pe3) can be used as a general - purpose i/o port. similarly, w hen using an external cloc k as an input of the sub clock , set x0 a/ x1 a to the external clock input, and input the clock to x0 a. x1 a (p47) can be used as a general - purpose i/o port. ? example of using an external clock device x0 ( x0a ) x1 (pe3), x1a (p47) can be used as general - purpose i/o ports. set as external clock input
document number: 002 - 05661 rev. *d page 54 of 131 mb9b520ta series handling when using multi - function serial pin as i 2 c pin if it is using the multi - function serial pin as i 2 c pins, p - ch transistor of digital output is always disable d . however, i 2 c pins need to keep the electrical characteristic like other pins and not to connect to the external i 2 c bus system with power off. c pin this series contains the regulator. be sure to connect a smoothing capacitor (c s ) for the regulator between the c pin and the gnd pin. please use a ceram ic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. however, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (f characteristics and y5v characteristic s). please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. a smoothing capacitor of about 4.7 f would be recommended for this series. mode pins (md0) connect the md pin (md0) directly to v cc or v ss pins. design the printed circuit board such that the pull - up/down resistance stays low, as well as the distance between the mode pins and v cc pins or v ss pi ns is as short as possible and the connection impedance is low, when the pins are pulled - up/down such as for switching the pin level and rewriting the flash memory data. it is because of preventing the device erroneously switching to test mode due to noise . notes on power - on turn power on/off in the following order or at the same time. if not using the a/d converter and d/a converter, connect avcc = vcc and avss = vss. turning on : vcc usbvcc v cc avcc avrh turning off : avrh avcc vcc usbvcc vcc serial communication there is a possibility to receive wrong data due to the noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. if an error is detected , retransmit the data. differences in features among the products with different memory sizes and between flash memory products and mask products the electric characteristics including power consumption, esd, latch - up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between flash memory products and mask products are different because chip layout and mem ory structures are different. if you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics . device c vss c s gnd
document number: 002 - 05661 rev. *d page 55 of 131 mb9b520ta series pull - up function of 5 v tolerant i/o please do not input the signal more than vcc voltage at the time of pull - up function use of 5v tolerant i / o. adjoining wiring on circuit board if wiring of the crystal oscillation circuit (x0/x1 and x0a/ x1a ) adjoins and also runs in parallel with the wiring of gpio , there is a possibility that the oscillation erron eously counts because oscillation wave has noise with the change of gpio . keep as much distance as possible between both wirings and insert the ground pattern between them in order to avoid this possibility.
document number: 002 - 05661 rev. *d page 56 of 131 mb9b520ta series 8. block diagram (host /device) m u l t i - l a y e r a h b ( m a x 6 0 m h z ) a h b - a p b b r i d g e : a p b 0 ( m a x 3 2 m h z ) c o r t e x - m 3 f l a s h i / f c l o c k r e s e t g e n e r a t o r d u a l - t i m e r w a t c h d o g t i m e r ( h a r d w a r e ) d m a c 8 c h . w a t c h c o u n t e r u n i t 0 c s v e x t e r n a l i n t e r r u p t c o n t r o l l e r 3 2 p i n + n m i p o w e r - o n r e s e t s r a m 0 8 0 / 9 6 k b y t e s s r a m 1 8 0 / 9 6 k b y t e s i d s y s c l k n v i c w a t c h d o g t i m e r ( s o f t w a r e ) s e c u r i t y u n i t 1 t r s t x , t c k , t d i , t m s t r a c e d x , t r a c e c l k x 0 a v c c , a v s s , a v r h a n x x t i o a x t i o b x c t d o x 1 x 0 a x 1 a s c k x s i n x s o t x i n t x n m i x p 0 x , p 1 x , . . . p f x i n i t x m o d e - c t r l i r q - m o n i t o r m d 0 , m d 1 r e g u l a t o r c r c a c c e l e r a t o r a d t g x r t s 4 c t s 4 m a d x m a d a t a x o n - c h i p f l a s h 1 m b y t e s + 6 4 k b y t e s / 1 . 5 m b y t e s + 6 4 k b y t e s m u l t i - f u n c t i o n s e r i a l i / f 1 6 c h . h w f l o w c o n t r o l ( c h . 4 ) e x t e r n a l b u s i / f g p i o p i n - f u n c t i o n - c t r l l v d t p i u r o m t a b l e e t m s w j - d p m a i n o s c p l l s u b o s c c r 4 m h z c r 1 0 0 k h z c e c 0 _ x , c e c 1 _ x l v d c t r l b a s e t i m e r 1 6 - b i t 1 6 c h . / 3 2 - b i t 8 c h . h d m i - c e c / r e m o t e r e c i v e r c o n t r o l r e a l - t i m e c l o c k r t c c o , s u b o u t d e e p s t a n d b y c t r l w k u p x 1 6 - b i t f r e e - r u n t i m e r 3 c h . 1 6 - b i t o u t p u t c o m p a r e 6 c h . 1 6 - b i t i n p u t c a p t u r e 4 c h . a / d a c t i v a t i o n c o m p a r e 2 c h . 1 6 - b i t p p g 3 c h . d t t i 0 x f r c k 0 q p r c 2 c h . b i n x z i n x i c 0 x r t o 0 x a i n x 1 2 - b i t a / d c o n v e r t e r m u l t i - f u n c t i o n t i m e r 1 m c s x x , m d q m x , m o e x , m w e x , m a l e , m r d y , m n a l e , m n c l e , m n w e x , m n r e x , m c l k o u t i g t r g x w a v e f o r m g e n e r a t o r 3 c h . c r o u t s o u r c e c l o c k u d p 0 / u d m 0 u h c o n x u s b 2 . 0 ( h o s t / f u n c ) p h y c a n 1 c h . t x 0 _ x , r x 0 _ x u s b c l o c k c t r l p l l c a n p r e s c a l e r 1 0 - b i t d / a c o n v e r t e r 2 u n i t s d a x a h b - a h b b r i d g e a h b - a p b b r i d g e : a p b 1 ( m a x 3 2 m h z ) a h b - a p b b r i d g e : a p b 2 ( m a x 3 2 m h z )
document number: 002 - 05661 rev. *d page 57 of 131 mb9b520ta series 9. memory size see memory size in 1 . p roduct l ineup to confirm the memory size. 10. memory map memory map (1) peripherals area 0x41ff_ffff 0xffff_ffff 0xe010_0000 0x4006_3000 0xe000_0000 0x4006_2000 can ch.0 0x4006_1000 reserved 0x4006_0000 dmac 0x4005_0000 reserved 0x4004_0000 usb ch.0 0x4003_f000 ext-bus i/f 0x4003_c000 reserved 0x7000_0000 0x4003_b000 rtc 0x4003_a000 watch counter 0x6000_0000 0x4003_9000 crc 0x4003_8000 mfs 0x4003_7000 can prescaler 0x4400_0000 0x4003_6000 usb clock ctrl 0x4003_5000 lvd/ds mode 0x4200_0000 0x4003_4000 hdmi-cec/ remote control receiver 0x4003_3000 gpio 0x4000_0000 0x4003_2000 reserved 0x4003_1000 int-req.read 0x2400_0000 0x4003_0000 exti 0x4002_f000 reserved 0x2200_0000 0x4002_e000 cr trim 0x4002_9000 reserved 0x2001_8000 0x4002_8000 d/ac 0x2000_0000 sram1 0x4002_7000 a/dc 0x1ffe_8000 sram0 0x4002_6000 qprc 0x4002_5000 base timer 0x0051_8000 0x4002_4000 ppg 0x0050_8000 flash(work area) 0x0040_4000 reserved 0x0040_0000 security/cr trim 0x4002_1000 0x4002_0000 mft unit0 0x4001_6000 0x4001_5000 dual timer 0x0000_0000 0x4001_3000 0x4001_2000 sw wdt 0x4001_1000 hw wdt 0x4001_0000 clock/reset 0x4000_1000 0x4000_0000 flash i/f 32mbytes bit band alias see " l memory map(2)" for the memory size details. reserved peripherals reserved 32mbytes bit band alias reserved reserved flash(main area) reserved reserved reserved reserved reserved cortex-m3 private peripherals reserved reserved external device area
document number: 002 - 05661 rev. *d page 58 of 131 mb9b520ta series memory map (2) the content of sram can be retained at the deep standby modes by the setting of deep standby ram retention register (dsramr). see "mb9b520t/420t/320t/120t series flash p rogramming m anual " for sector s tructure of flash. rom1_sa8_15(64kbx8) mb9bf529sa/ta mb9bf528sa/ta 0x2008_0000 0x2008_0000 0x2001_8000 0x2001_4000 0x2000_4000 0x2000_4000 0x2000_0000 sram1 16kbytes* 0x2000_0000 sram1 16kbytes* 0x1fff_c000 sram0 16kbytes* 0x1fff_c000 sram0 16kbytes* 0x1ffe_c000 0x1ffe_8000 0x0051_8000 0x0051_8000 0x0050_8000 0x0050_8000 0x0040_4000 0x0040_4000 0x0040_2000 cr trimming 0x0040_2000 cr trimming 0x0040_0000 security 0x0040_0000 security 0x0018_0000 reserved 0x0010_0000 0x0010_0000 rom0_sa8(48kb) rom0_sa8(48kb) 0x0000_0000 rom0_sa2-3(8kbx2) 0x0000_0000 rom0_sa2-3(8kbx2) rom0_sa9-23(64kbx15) reserved reserved reserved reserved reserved rom1_sa0-7(8kbx8) rom1_sa0-7(8kbx8) sram0 64kbytes sram1 64kbytes sram1 80kbytes sram0 80kbytes reserved rom1_sa8-15(8kbx8) reserved flash (work area, rom1) 64kbytes flash (work area, rom1) 64kbytes flash (main area, rom0) 1mbytes flash (main area, rom0) 1mbytes flash (main area, rom1) 512kbytes rom0_sa9-23(64kbx15)
document number: 002 - 05661 rev. *d page 59 of 131 mb9b520ta series peripheral address map start address end address bus peripherals 0x4000_0000 0x4000_0fff ahb flash memory i/f register 0x4000_1000 0x4000_ffff reserved 0x4001_0000 0x4001_0fff apb0 clock/reset control 0x4001_1000 0x4001_1fff hardware watchdog timer 0x4001_2000 0x4001_2fff software watchdog timer 0x4001_3000 0x4001_4fff reserved 0x4001_5000 0x4001_5fff dual - timer 0x4001_6000 0x4001_ffff reserved 0x4002_0000 0x4002_0fff apb1 multi - function timer unit 0 0x4002_1000 0x4002_ 3 fff reserved 0x4002_4000 0x4002_4fff ppg 0x4002_5000 0x4002_5fff base timer 0x4002_6000 0x4002_6fff quadrature position/revolution counter (qprc) 0x4002_7000 0x4002_7fff a/d converter 0x4002_8000 0x4002_8 fff d /a converter 0x4002_ 9 000 0x4002_dfff reserved 0x4002_e000 0x4002_efff built - in cr trimming 0x4002_f000 0x4002_ffff reserved 0x4003_0000 0x4003_0fff apb2 external interrupt 0x4003_1000 0x4003_1fff interrupt source check resister 0x4003_2000 0x4003_2fff reserved 0x4003_3000 0x4003_3fff gpio 0x4003_4000 0x4003_4fff hdmi - cec/remote control reception 0x4003_5000 0x4003_5 7 ff low - voltage detector 0x4003_ 58 00 0x4003_5 f ff deep standby mode controller 0x4003_6000 0x4003_6fff usb clock generator 0x4003_7000 0x4003_7fff can prescaler 0x4003_8000 0x4003_8fff multi - function serial interface 0x4003_9000 0x4003_9fff crc 0x4003_a000 0x4003_afff watch counter 0x4003_b000 0x4003_ b fff real - time clock 0x4003_ c 000 0x4003_ e fff reserved 0x4003_ f 000 0x4003_ f fff external bus interface 0x4004_0000 0x4004_ffff ahb usb ch . 0 0x4005_0000 0x4005_ffff reserved 0x4006_0000 0x4006_0fff dmac register 0x4006_ 1 000 0x4006_ 1 fff reserved 0x4006_ 2 000 0x4006_ 2 fff can ch. 0 0x4006_ 3 000 0x41ff_ffff reserved
document number: 002 - 05661 rev. *d page 60 of 131 mb9b520ta series 11. pin status in each cpu state the terms used for pin status have the following meanings. ? initx=0 this is the period when the initx pin is the "l" level. ? initx=1 this is the period when the initx pin is the "h" level. ? spl=0 this is the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to "0". ? spl=1 this is the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to "1". ? in put enabled indicates that the input function can be used. ? internal input fixed at "0" this is the status that the input function cannot be used. internal input is fixed at "l". ? hi - z indicates that the pin drive transistor is disabled and the pin is put in the hi - z state. ? setting disabled indicates that the setting is disabled. ? maintain previous state maintains the state that was immediately prior to entering the current mode. if a built - in peripheral function is operating, the output follows the peripheral function. if the pin is being used as a port, that output is maintained. ? analog input is enabled indicates that the analog input is enabled. ? trace output indicates that the trace function can be used. ? gpio selected in deep standby mode, pins switch to the general - purpose i/o port.
document number: 002 - 05661 rev. *d page 61 of 131 mb9b520ta series list of pin status pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - a gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected main crystal oscillator input pin/ external main clock input selected input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled b gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected external main clock input selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" maintain previous state hi - z / internal input fixed at "0" maintain previous state main crystal oscillator output pin hi - z / internal input fixed at "0"/ or input enable hi - z / internal input fixed at "0" hi - z / internal input fixed at "0" maintain previous state/ when oscillation stop s * 1 , hi - z / internal input fixed at "0" maintain previous state/ when oscillation stop s * 1 , hi - z / internal input fixed at "0" maintain previous state/ when oscillation stop s * 1 , hi - z / internal input fixed at "0" maintain previous state/ when oscillation stop s * 1 , hi - z / internal input fixed at "0" maintain previous state/ when oscillation stop s * 1 , hi - z / internal input fixed at "0" maintain previous state/ when oscillation stop s * 1 , hi - z / internal input fixed at "0" c initx input pin pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled d mode input pin input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled
document number: 002 - 05661 rev. *d page 62 of 131 mb9b520ta series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - e mode input pin input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / input enabled gpio selected hi - z / input enabled gpio selected f gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected sub crystal oscillator input pin / external sub clock input selected input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled g gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected external sub clock input selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" maintain previous state hi - z/ internal input fixed at "0" maintain previous state sub crystal oscillator output pin hi - z / internal input fixed at " 0 " / or input enable hi - z / internal input fixed at "0" hi - z / internal input fixed at "0" maintain previous state maintain previous state / when oscillation stop s * 2 , hi - z / internal input fixed at "0" maintain previous state / when oscillation stop s * 2 , hi - z / internal input fixed at "0" maintain previous state / when oscillation stop s * 2 , hi - z / internal input fixed at "0" maintain previous state / when oscillation stop s * 2 , hi - z / internal input fixed at "0" maintain previous state / when oscillation stop s * 2 , hi - z / internal input fixed at "0"
document number: 002 - 05661 rev. *d page 63 of 131 mb9b520ta series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - h nmix selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state wkup input enabled hi - z / wkup input enabled gpio selected gpio selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0" i jtag selected hi - z pull - up / input enabled pull - up / input enabled maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state gpio selected setting disabled setting disabled setting disabled hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected j resource selected hi - z hi - z / input enabled hi - z / input enabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected gpio selected k external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0" gpio selected l analog input selected hi - z hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / int ernal input fixed at "0" / analog input enabled resource other than above selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected gpio selected
document number: 002 - 05661 rev. *d page 64 of 131 mb9b520ta series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - m analog input selected hi - z hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected resource other than above selected hi - z / internal input fixed at "0" gpio selected n analog input selected hi - z hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled h i - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled wkup enabled setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state wkup input enabled hi - z / wkup input enabled gpio selected external interrupt enabled selected gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" resource other than above selected hi - z / internal input fixed at "0" gpio selected
document number: 002 - 05661 rev. *d page 65 of 131 mb9b520ta series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - o analog out put selected setting disabled setting disabled setting disabled maintain previous state *3 *4 gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected resource other than above selected hi - z hi - z / input enabled hi - z / input enabled maintain previous state hi - z / internal input fixed at "0" gpio selected p trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0" gpio selected q trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected external interrupt enabled selected maintain previous state resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0" gpio selected r cec enabled setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected gpio selected
document number: 002 - 05661 rev. *d page 66 of 131 mb9b520ta series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - s cec enabled setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state external interrupt enabled selected gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0" gpio selected t cec enabled setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state wkup enabled wkup input enabled hi - z / wkup input enabled gpio selected external interrupt enabled selected gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0" gpio selected u wkup enabled setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state wkup input enabled hi - z / wkup input enabled gpio selected external interrupt enabled selected gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0" gpio selected
document number: 002 - 05661 rev. *d page 67 of 131 mb9b520ta series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode , rtc mode , or stop mode state deep standby rtc mode or deep standby stop mode state return from deep sta ndby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable - initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - - - spl = 0 spl = 1 spl = 0 spl = 1 - v gpio selected hi - z hi - z / input enabled hi - z / input enabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected usb i/o pin setting disabled setting disabled setting disabled hi - z at trans - mission/ input enabled/ internal input fixed at " 0 " at reception hi - z at trans - mission/ input enabled/ internal input fixed at " 0 " at reception hi - z / input enabled hi - z / input enabled hi - z / in put enabled *1: oscillation is stopped at s ub timer mode , low - speed cr timer mode, rtc mode, stop mode , deep standby rtc mode , and deep standby stop mode. *2: oscillation is stopped at stop mode and deep standby stop mode . *3: maintain previous state at timer mode . gpio selected internal input fixed at "0" at rtc mode , stop mode. *4: maintain previous state at timer mode . hi - z/ internal input fixed at "0" at rtc mode , stop mode.
document number: 002 - 05661 rev. *d page 68 of 131 mb9b520ta series 12. electrical characteristics 12.1 absolute maximum ratings parameter symbol rat ing unit remarks min max power supply voltage* 1, * 2 v cc v ss - 0.5 v ss + 6.5 v power supply voltage (for usb)* 1, * 3 usbv cc v ss - 0.5 v ss + 6.5 v analog power supply voltage* 1, * 4 av cc v ss - 0.5 v ss + 6.5 v analog reference voltage* 1, * 4 avrh v ss - 0.5 v ss + 6.5 v input voltage* 1 v i v ss - 0.5 v cc + 0.5 ( 6.5 v) v except for usb pin v ss - 0.5 usbv cc + 0.5 ( 6.5 v) v usb pin v ss - 0.5 v ss + 6.5 v 5v tolerant v ss - 0.5 v ss + 3. 6 3 v 5v tolerant * 8 analog pin input voltage* 1 v ia v ss - 0.5 av cc + 0.5 ( 6.5 v) v output voltage* 1 v o v ss - 0.5 v cc + 0.5 ( 6.5 v) v clamp maximum current i clamp - 2 +2 ma * 9 clamp total maximum current [i clamp ] +20 ma * 9 " l " level maximum output current* 5 i ol - 10 ma 4ma type 20 ma 12ma type 39 ma p80, p81 " l " level average output current* 6 i olav - 4 ma 4ma type 12 ma 12ma type 16.5 ma p80, p81 " l " level total maximum output current i ol - 100 ma " l " level total average output current* 7 i olav - 50 ma " h " level maximum output current* 5 i oh - - 10 ma 4ma type - 20 ma 12ma type - 39 ma p80, p81 " h " level average output current* 6 i ohav - - 4 ma 4ma type - 12 ma 12ma type - 18 ma p80, p81 " h " level total maximum output current i oh - - 100 ma " h " level total average output current* 7 i ohav - - 50 ma power consumption p d - 3 9 0 mw storage temperature t stg - 55 + 150 c *1: these parameters are based on the condition that v ss = av ss = 0 v. *2: v cc must not drop below v ss - 0.5 v. *3: usbv cc must not drop below v ss - 0.5 v. *4: ensure that the voltage does not exceed v cc + 0. 5 v, for example, when the power is turned on. *5: the maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins . *6: the average output current is defined as the average current value flowing through any one of the corresponding pins for a 100 ms period. *7: the total average output current is defined as the average current value flowing throu gh all of corresponding pins for a 100 ms. *8: v cc = usb v cc = av cc = av rh = v ss = av ss = av rl = 0 .0 v
document number: 002 - 05661 rev. *d page 69 of 131 mb9b520ta series *9 : ? see 4 . list of pin functions and 5 . i/o circuit type about +b input available pin. ? use within recommended operating conditions. ? use at dc voltage (current) the +b input. ? the +b signal should always be applied a limiting resistance placed between the +b signal and the device. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the devi ce pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the device drive current is low, such as in the low - power consumption modes, the +b input potential may pass through the protective diode and increase the potential at the v cc and avcc pin, and this may affect other devices. ? note that if a +b signal is input when the device power supply is off (not fixed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? the follow ing is a r ecommended circuit example (i/o equivalent circuit ) . warning : ? semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. do not exceed any of these ratings. r p - ch v cc v cc limiting resistor n - ch av cc analog input digital input digital output +b input (0v to 16v) protection diode
document number: 002 - 05661 rev. *d page 70 of 131 mb9b520ta series 12.2 recommended operating conditions (v ss = av ss = 0.0v) parameter symbol conditions value unit remarks min max power supply voltage v cc - 2.7* 4 5.5 v power supply voltage (3v power supply) for usb usbv cc - 3.0 3.6 ( v cc ) v * 1 2.7 5.5 ( v cc ) * 2 analog power supply voltage av cc - 2.7 5.5 v av cc = v cc analog reference voltage avrh - 2.7 av cc v avrl - av ss av ss v smoothing capacitor c s - 1 10 f for built - in regulator * 3 operating temperature t a - - 40 + 105 c *1: when p81/udp0 and p80/udm0 pins are used as usb (udp0, udm0). *2: when p81/udp0 and p80/udm0 pins are used as gpio (p81, p80). *3 : see c pin in 7 . handling devices for the connection of the smoothing capacitor. *4: in between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage or more, instruction execution and low voltage detection function by built - in high - speed cr (including main pll is used) or built - in low - speed cr is possible to operate only. w arning : ? the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated under these conditions. any use of semic onductor devices will be under their recommended operating condition. operation under any conditions other than these conditions may adversely affect reliability of device and could result in dev ice failure. no warranty is made with respect to any use, ope rating conditions or combinations not represented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
document number: 002 - 05661 rev. *d page 71 of 131 mb9b520ta series 12.3 dc characteristics 12.3.1 current rating parameter symbol (pin name) conditions value unit remarks typ* 1 max* 2 power supply current i cc pll run mode cpu: 60 mhz , peripheral: 3 0 mhz * 3 ,* 5 29 37 ma cpu: 60 mhz, peripheral clock stops * 3 ,* 5 19 26 ma high - speed cr run mode cpu/ peripheral: 4 mhz* 4 * 3 3.1 6.4 ma sub run mode cpu/ peripheral: 32 khz * 3 ,* 6 170 2300 a low - speed cr run mode cpu/ peripheral: 100 khz * 3 210 2300 a i ccs pll sleep mode peripheral: 3 0 mhz * 3 ,* 5 19 26 ma high - speed cr sleep mode peripheral: 4 mhz* 4 * 3 2.1 5.1 ma sub sleep mode peripheral: 32 khz * 3 ,* 6 160 2200 a low - speed cr sleep mode peripheral: 100 khz * 3 190 2200 a i cc h stop mode t a = + 25 c * 3 20 75 a t a = + 105 c * 3 - 1.3 m a i cc t main timer mode t a = + 25 c * 3 ,* 6 2.8 5.5 m a t a = + 105 c * 3 ,* 6 - 6.5 m a sub timer mode t a = + 25 c * 3 ,* 6 24 95 a t a = + 105 c * 3 ,* 6 - 1.7 m a i cc r rtc mode t a = + 25 c * 3 ,* 6 21 89 a t a = + 105 c * 3 ,* 6 - 1.7 m a *1 : t a =+25 c , v cc = 3.3 v *2: t a =+105 c , v cc = 5.5 v *3: when all ports are fixed. *4: when setting it to 4 mhz by trimming. *5: when using the crystal oscillator of 4 mhz (including the current consumption of the oscillation circuit) *6: when using the crystal oscillator of 32 khz (including the current consumption of the oscillation circuit)
document number: 002 - 05661 rev. *d page 72 of 131 mb9b520ta series parameter symbol (pin name) conditions value unit remarks typ* 1 max* 2 power supply current i cc h d deep standby stop mode t a = + 25 c , when ram is off * 3 1.9 13 a t a = + 25 c , when ram is on (16 kb)* 4 * 3 4.8 17 a t a = + 25 c , when ram is on (32 kb) * 4 * 3 5.5 20 a t a = + 105 c , when ram is off * 3 - 300 a t a = + 105 c , when ram is on (16 kb) * 4 * 3 320 a t a = + 105 c , when ram is on ( 32 kb) * 4 * 3 330 a i cc rd deep standby rtc mode t a = + 25 c , when ram is off * 3 ,* 5 2.5 14 a t a = + 25 c , when ram is on (16 kb) * 4 * 3 ,* 5 5.4 18 a t a = + 25 c , when ram is on ( 32 kb) * 4 * 3 ,* 5 6.1 21 a t a = + 105 c , when ram is off * 3 ,* 5 - 305 a t a = + 105 c , when ram is on (16 kb) * 4 * 3 ,* 5 325 a t a = + 105 c , when ram is on ( 32 kb) * 4 * 3 ,* 5 335 a *1: v cc = 3.3 v *2: v cc = 5.5 v * 3 : when a l l ports are fixed and lvd o ff . * 4 : for more information about ram retention area, s ee " memory map (2) " in " 10 . memory map " . * 5 : when using the crystal oscillator of 32 khz (including the current consumption of the oscillation circuit )
document number: 002 - 05661 rev. *d page 73 of 131 mb9b520ta series low - voltage detection current ( v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 105 c) parameter symbol ( pin name ) conditions value unit remarks min typ max low - voltage detection circuit (lvd) power supply current i cclvd ( vcc ) at operation - 0.13 0.3 a for occurrence of reset - 0.1 3 0.3 a for occurrence of interrupt flash memory current ( v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks min typ max flash memory write/erase current i ccflash (vcc) vcc at rom0 write/erase - 9.9 11.8 ma *1 at rom 1 write/erase - 9.5 11.2 ma * 1 * 1 : wh en programming or erase in flash memory, flash memory write/erase current (iccflash) is added to the power supply current (i cc ). in addition, w hen programming or erase in flash memory rom0 and rom1 at t he same time , flash memory write/erase current (iccflash) of both rom0 and rom1 are added to the power supply current (i cc ). a/d converter current ( v cc = av cc = 2.7v to 5.5v, v ss = av ss = avrl = 0v, t a = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks min typ max power supply current i ccad (vcc) a vcc at 1unit operation - 0. 69 0.9 ma at stop - 0. 6 35 a reference power supply current (avrh ) i ccavrh (vcc) avrh at 1unit operation avrh=5.5 v - 1.1 1.97 ma at stop - 0. 2 3.4 a
document number: 002 - 05661 rev. *d page 74 of 131 mb9b520ta series d/a converter current ( v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40c to + 105 c) parameter symbol pin name conditions value unit remarks min typ max power supply current * 1 i dda * 2 (vcc) avcc at 1unit operation av cc =3.3 v 250 315 380 a at 1unit operation av cc =5.0 v 380 475 580 a i dsa (vcc) at stop - - 30 a *1: no - load *2: generates the max current by the code about 0x200
document number: 002 - 05661 rev. *d page 75 of 131 mb9b520ta series 12.3.2 pin characteristics (v cc = usbv cc = av cc = 2.7v to 5.5v, v ss = av ss = avrl = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions value unit remarks min typ max "h" level input voltage (hysteresis input) v ihs cmos hysteresis input pin , md0 , md1 - v cc 0.8 - v cc + 0.3 v 5v tolerant input pin - v cc 0.8 - v ss + 5.5 v "l" level input voltage (hysteresis input) v ils cmos hysteresis input pin , md0 , md1 - v ss - 0.3 - v cc 0.2 v 5v tolerant input pin - v ss - 0.3 - v cc 0.2 v "h" level output voltage v oh 4ma type v cc 4.5 v , i oh = - 4 ma v cc - 0.5 - v cc v v cc < 4.5 v , i oh = - 2 ma 12ma type v cc 4.5 v , i oh = - 12 ma v cc - 0.5 - v cc v v cc < 4.5 v , i oh = - 8 ma p80, p81 usbv cc 4.5 v , i oh = - 18.0 ma usbv cc - 0.4 - usbv cc v usbv cc < 4.5 v , i oh = - 12.0 ma "l" level output voltage v ol 4ma type v cc 4.5 v , i ol = 4 ma v ss - 0.4 v v cc < 4.5 v , i ol = 2 ma 12ma type v cc 4.5 v , i ol = 12 ma v ss - 0.4 v v cc < 4.5 v , i ol = 8 ma p80, p81 usbv cc 4.5 v , i ol = 16.5 ma v ss - 0.4 v usbv cc < 4.5 v , i ol = 10.5 ma input leak current i il - - - 5 - + 5 a cec0_0, cec0_1, cec1_0, cec1_1 v cc = usb v cc = av cc = av rh = v ss = av ss = av rl = 0 .0 v - - +1.8 a pull - up resistance value r pu pull - up pin v cc 4.5 v 33 50 90 k v cc < 4.5 v - - 180 input capacitance c in other than vcc, usbvcc, vss, avcc, avss, avrh, avrl - - 5 15 pf
document number: 002 - 05661 rev. *d page 76 of 131 mb9b520ta series 12.4 ac characteristics 12.4.1 main clock input characteristics (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions value unit remarks min max input frequency f ch x0 , x1 v cc 4.5 v 4 48 mhz when crystal oscillator is connected v cc < 4.5 v 4 20 - 4 48 mhz when using external c lock input clock cycle t cylh - 20.83 250 ns when using external c lock input clock pulse width - p wh /t cylh , p wl /t cylh 45 55 % when using external c lock input clock rising time and falling time t cf , t cr - - 5 ns when using external c lock internal operating c lock * 1 frequency f cm - - - 60 mhz master clock f cc - - - 60 mhz base clock (hclk/fclk) f cp0 - - - 32 mhz apb0 bus clock* 2 f cp1 - - - 32 mhz apb1 bus clock* 2 f cp 2 - - - 32 mhz apb2 bus clock* 2 internal operating clock * 1 cycle time t cy cc - - 1 6.7 - ns base clock (hclk/fclk) t cycp 0 - - 31.25 - ns apb0 bus clock* 2 t cycp 1 - - 31.25 - ns apb1 bus clock* 2 t cycp 2 - - 31.25 - ns apb2 bus clock* 2 *1: for more information about each internal operating clock, see chapter 2 - 1 : clock in fm3 family peripheral manual . *2: for about each apb bus which each peripheral is connected to, see 8 . block diagram in this data sheet. x0
document number: 002 - 05661 rev. *d page 77 of 131 mb9b520ta series 12.4.2 sub clock input characteristics (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions value unit remarks min typ max input frequency 1/ t cyll x0a , x1a - - 32.768 - khz when crystal oscillator is connected * - 32 - 100 khz when using external clock input clock cycle t cyll - 10 - 31.25 s when using external clock input clock pulse width - p wh /t cyll , p wl /t cyll 45 - 55 % when using external clock *: for more information about crystal oscillator , see " sub crystal oscillator " in " 7 . handling devices " . x0 a
document number: 002 - 05661 rev. *d page 78 of 131 mb9b520ta series 12.4.3 built - in cr oscillation characteristics built - in high - speed cr (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol conditions value unit remarks min typ max clock frequency f crh t a = + 25 c , 3.6 v < v cc 5.5 v 3.9 2 4 4.0 8 mhz when trimming * 1 t a = 0 c to + 85 c , 3.6 v < v cc 5.5 v 3.9 4 4.1 t a = - 40 c to + 105 c , 3.6 v < v cc 5.5 v 3.88 4 4.12 t a = + 25 c , 2.7 v v cc 3.6 v 3.94 4 4.06 t a = - 20c to + 85 c , 2.7 v v cc 3.6 v 3.92 4 4.08 t a = - 20c to + 105 c , 2.7 v v cc 3.6 v 3.9 4 4.1 t a = - 40 c to + 105 c , 2.7 v v cc 3.6 v 3.88 4 4.12 t a = - 40 c to + 105 c 2.8 4 5.2 when not trimming f requency stability time t crwt - - - 30 s * 2 * 1 : in the case of using the values in cr trimming area of flash memory at shipment for frequency/t emperature trimming. *2: f requency stable time is time to stable of the frequency of the high - speed cr . clock after the trim value is set. after setting the trim value, the period when the frequency stability time passes can use the high - speed cr clock as a source clock. built - in low - speed cr (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol conditions value unit remarks min typ max clock frequency f crl - 50 100 150 khz
document number: 002 - 05661 rev. *d page 79 of 131 mb9b520ta series 12.4.4 operating conditions of main and usb pll (in the case of using main clock for input of pll) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time* 1 (lock up time) t lock 100 - - s pll input clock frequency f plli 4 - 16 mh z pll multiplication rate - 5 - 37 multiplier pll macro oscillation clock frequency f pllo 75 - 150 mh z main pll clock frequency* 2 f clkpll - - 60 mh z usb clock frequency* 3 f clkspll - - 48 mh z after the m frequency division *1: time from when the pll starts ope rating until the oscillation stabilizes. *2: for more information about main pll clock (clkpll), see " c hapter 2 - 1 : clock" in "fm3 family peripheral manual". *3: for more information about usb clock, see " c hapter 2 - 2 : usb clock generation" in "fm3 family peripheral manual communication macro part". 12.4.5 operating conditions of main pll (in the case of using built - in high - speed cr for input clock of main pll) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time* 1 (lock up time) t lock 100 - - s pll input clock frequency f plli 3.8 4 4.2 mh z pll multiplication rate - 19 - 35 multiplier pll macro oscillation clock frequency f pllo 72 - 150 mh z main pll clock frequency* 2 f clkpll - - 60 mh z *1: time from when the pll starts operating until the oscillation stabilizes. *2: for more information about main pll clock (clkpll), see " c hapter 2 - 1 : clock" in "fm3 family peripheral manual". note: ? make sure to input to the main pll source clock, the high - speed cr clock (clkhc) that the frequency / t emperature has been trimmed.
document number: 002 - 05661 rev. *d page 80 of 131 mb9b520ta series k divider pll input clock main pll pll macro oscillation clock m divider main pll clock (clkpll) n divider main pll connection main clock (clkmo) high - speed cr clock (clkhc) main clock (clkmo) k divider pll input clock usb pll m divider usb clock n divider usb pll connection pll macro oscillation clock
document number: 002 - 05661 rev. *d page 81 of 131 mb9b520ta series 12.4.6 reset input characteristics (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions value unit remarks min max reset input time t initx initx - 500 - n s 12.4.7 power - on reset timing (v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions value unit remarks min typ max power supply shut down time t off vcc - 1 - ms *1 power ramp rate dv/dt v cc : 0.2 v to 2.70 v 0.9 1000 mv/ / s *2 time until releasin g p ower - on reset t prt - 0.46 0.76 ms *1: vcc must be held below 0.2 v for minimum period of t off . improper initialization may occur if this condition is not met. *2: this dv/dt characteristic is applied at the power - on of cold start (t off > 1ms). note: ? if t off cannot be satisfied designs must assert external reset (intx) at power - up and at any brownout event p er 12.4.6. glossary vdh : detection voltage of low voltage detection reset. see 12.8. low - voltage detection characteristics v d h t p r t i n t e r n a l r s t v c c c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e 0 . 2 v 0 . 2 v t o f f d v / d t 0 . 2 v 2 . 7 v
document number: 002 - 05661 rev. *d page 82 of 131 mb9b520ta series 12.4.8 external bus timing external bus clock output characteristics (v cc = 2.7 v to 5.5 v, v ss = 0v, t a = - 40c to + 10 5c) parameter symbol pin name conditions value unit min max out put frequency t cycle mclkout * v cc 4.5 v - 5 0 mhz v cc < 4.5 v - 32 mhz * : the external bus clock (mclkout) is a divided clock of hclk. for more information about setting of clock divider , see " c hapter 1 2 : external bus interface " in "fm3 family peripheral manual ". when external bus clock is not output, this characteristic does not give any effect on external bus operation. external bus signal input/output characteristics (v cc = 2.7 v to 5.5 v, v ss = 0v, t a = - 40c to + 10 5c) parameter symbol conditions value unit remarks signal input c haracteristics v ih - 0.8 v cc v v il 0.2 v cc v signal output c haracteristics v oh 0.8 v cc v v ol 0.2 v cc v input signal output signal mclkout v ih v il v il v ih v oh v ol v ol v oh
document number: 002 - 05661 rev. *d page 83 of 131 mb9b520ta series separate bus access asynchronous sram mode (v cc = 2.7 v to 5.5 v, v ss = 0v, t a = - 40c to + 10 5c) parameter symbol pin name conditions value unit min max moex min pulse width t oew moex v cc 4.5 v mclk n - 3 - ns v cc < 4.5 v mcsx address output delay time t csl C av mcsx[7:0] , mad[24:0] v cc 4.5 v - 9 + 9 ns v cc < 4.5 v - 12 + 12 moex address hold time t oeh - ax moex , mad[24:0] v cc 4.5 v 0 mclk m+9 ns v cc < 4.5 v mclk m+12 mcsx moex delay time t cs l - oe l moex , mcsx[7:0] v cc 4.5 v mclk m - 9 mclk m+9 ns v cc < 4.5 v mclk m - 12 mclk m+12 moex mcsx time t oeh - c sh v cc 4.5 v 0 mclk m+9 ns v cc < 4.5 v mclk m+12 mcsx mdqm delay time t cs l - r dqml mcsx , mdqm[1:0] v cc 4.5 v mclk m - 9 mclk m+9 ns v cc < 4.5 v mclk m - 12 mclk m+12 data set up moex time t ds - oe moex , madata[15:0] v cc 4.5 v 2 0 - ns v cc < 4.5 v 38 - moex data hold time t dh - oe moex , madata[15:0] v cc 4.5 v 0 - ns v cc < 4.5 v m wex min pulse width t wew mwex v cc 4.5 v mclk n - 3 - ns v cc < 4.5 v mwex address output delay time t weh - ax mwex , mad[24:0] v cc 4.5 v 0 mclk m+9 ns v cc < 4.5 v mclk m+12 mcsx mwex delay time t csl - wel mwex , mcsx[7:0] v cc 4.5 v mclk n - 9 mclk n+9 ns v cc < 4.5 v mclk n - 12 mclk n+12 mwex mcsx delay time t weh - csh v cc 4.5 v 0 mclk m+9 ns v cc < 4.5 v mclk m+12 mcsx mdqm delay time t cs l - w dqml mcsx , mdqm[1:0] v cc 4.5 v mclk n - 9 mclk n+9 ns v cc < 4.5 v mclk n - 12 mclk n+12 mcsx data output time t cs l - dv mcsx , madata[15:0] v cc 4.5 v mclk - 9 mclk +9 ns v cc < 4.5 v mclk - 12 mclk +12 mwex data hold time t weh - dx mwex , madata[15:0] v cc 4.5 v 0 mclk m+ 12 ns v cc < 4.5 v note: ? w hen the external load capacitance c l = 30 pf (m = 0 to 15, n = 1 to 16).
document number: 002 - 05661 rev. *d page 84 of 131 mb9b520ta series mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex i n v a l i d a d d r e s s t c s l - o e l t c s l - a v r d a d d r e s s w d t d h - o e t d s - o e t w e h - d x t o e w t o e h - a x t o e h - c s h t w e w t c y c l e t c s l - w e l t c s l - a v t w e h - c s h t w e h - a x t c s l - w d q m l t c s l - r d q m l t c s l - d v
document number: 002 - 05661 rev. *d page 85 of 131 mb9b520ta series separate bus access synchronous sram mode (v cc = 2.7 v to 5.5 v, v ss = 0v, t a = - 40c to + 10 5c) parameter symbol pin name conditions value unit min max address delay time t av mclk , mad[24:0] v cc 4.5 v 1 12 ns v cc < 4.5 v mcsx delay time t csl mclk , mcsx[7:0] v cc 4.5 v 1 9 ns v cc < 4.5 v 12 t cs h v cc 4.5 v 1 9 ns v cc < 4.5 v 12 moex delay time t rel mclk , moex v cc 4.5 v 1 9 ns v cc < 4.5 v 12 t reh v cc 4.5 v 1 9 ns v cc < 4.5 v 12 data set up mclk time t ds mclk , madata[15:0] v cc 4.5 v 19 - ns v cc < 4.5 v 37 mclk data hold time t dh mclk , madata[15:0] v cc 4.5 v 0 - ns v cc < 4.5 v mwex delay time t wel mclk , mwex v cc 4.5 v 1 9 ns v cc < 4.5 v 12 t we h v cc 4.5 v 1 9 ns v cc < 4.5 v 12 mdqm[1:0] delay time t dqml mclk , mdqm[1:0] v cc 4.5 v 1 9 ns v cc < 4.5 v 12 t dqmh v cc 4.5 v 1 9 ns v cc < 4.5 v 12 mclk data output time t od s mclk , madata[15:0] v cc 4.5 v mclk+ 1 mclk+ 18 ns v cc < 4.5 v mclk+ 24 mclk data hold time t od mclk , madata[15:0] v cc 4.5 v 1 18 ns v cc < 4.5 v 24 note: ? w hen the external load capacitance c l = 30 pf. mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex moex madata[15:0] i n v a l i d t d q m l t r e h a d d r e s s t c s l t a v t r e l r d a d d r e s s w d t d q m h t w e h t w e l t d h t d s t o d t a v t c s h t c y c l e t d q m l t d q m h t o d s
document number: 002 - 05661 rev. *d page 86 of 131 mb9b520ta series multiplexed bus access asynchronous sram mode (v cc = 2.7 v to 5.5 v, v ss = 0v, t a = - 40c to + 10 5c) parameter symbol pin name conditions value unit min max multiplexed a ddress delay time t a le - chmadv male , madata[15:0] v cc 4.5 v 0 + 10 ns v cc < 4.5 v + 20 multiplexed a ddress hold time t c hmadh v cc 4.5 v mclk n+0 mclk n+1 2 ns v cc < 4.5 v mclk n+0 mclk n+20 note: ? w hen the external load capacitance c l = 30 pf (m = 0 to 15, n = 1 to 16) . mclk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0]
document number: 002 - 05661 rev. *d page 87 of 131 mb9b520ta series multiplexed bus access synchronous sram mode (v cc = 2.7 v to 5.5 v, v ss = 0v, t a = - 40c to + 10 5c) parameter symbol pin name conditions value unit remarks min max male delay time t chal mclk , ale v cc 4.5 v 1 9 ns v cc < 4.5 v 1 2 ns t chah v cc 4.5 v 1 9 ns v cc < 4.5 v 12 ns mclk multiplexed address delay time t chmadv m clk , madata[15:0] v cc 4.5 v 1 t od ns v cc < 4.5 v mclk multiplexed data output time t chmad x v cc 4.5 v 1 t od ns v cc < 4.5 v note: ? w hen the external load capacitance c l = 30 pf. mclk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0]
document number: 002 - 05661 rev. *d page 88 of 131 mb9b520ta series nand flash memory mode (v cc = 2.7 v to 5.5 v, v ss = 0v, t a = - 40c to + 10 5c) parameter symbol pin name conditions value unit min max mnrex min pulse width t nrew mnrex v cc 4.5 v mclkn - 3 - ns v cc < 4.5 v data setup mnrextime t ds C nre mnrex, madata[15:0] v cc 4.5 v 20 - ns v cc < 4.5 v 38 - mnrex data hold time t dh C nre mnrex, madata[15:0] v cc 4.5 v 0 - ns v cc < 4.5 v mnale mnwex delay time t aleh - nwel mnale, mnwex v cc 4.5 v mclkm - 9 mclkm+9 ns v cc < 4.5 v mclkm - 12 mclkm+12 mnale mnwex delay time t alel - nwel mnale, mnwex v cc 4.5 v mclkm - 9 mclkm+9 ns v cc < 4.5 v mclkm - 12 mclkm+12 mncle mnwex delay time t cleh - nwel mncle, mnwex v cc 4.5 v mclkm - 9 mclkm+9 ns v cc < 4.5 v mclkm - 12 mclkm+12 mnwex mncle delay time t nweh - clel mncle, mnwex v cc 4.5 v 0 mclkm+9 ns v cc < 4.5 v mclkm+12 mnwex min pulse width t nwew mnwex v cc 4.5 v mclkn - 3 - ns v cc < 4.5 v mnwex data output time t nwel C dv mnwex, madata[15:0] v cc 4.5 v - 9 + 9 ns v cc < 4.5 v - 12 +12 mnwex data hold time t nweh C dx mnwex, madata[15:0] v cc 4.5 v 0 mclkm+ 11 ns v cc < 4.5 v mclkm+12 note: ? w hen the external load capacitance c l = 30 pf (m=0 to 15, n=1 to 16). nand f lash memory read mclk mnrex madata [ 15 : 0 ] read
document number: 002 - 05661 rev. *d page 89 of 131 mb9b520ta series nand flash memory a ddress w rite nand flash memory command write mclk mnale mncle madata [ 15 : 0 ] mnwex write mclk mnale mncle madata [ 15 : 0 ] mnwex write
document number: 002 - 05661 rev. *d page 90 of 131 mb9b520ta series external ready input timing (v cc = 2.7 v to 5.5 v, v ss = 0v, t a = - 40c to + 10 5c) parameter symbol pin name conditions value unit remarks min max mclk mrdy input setup time t rdyi mclk , mrdy v cc 4.5 v 19 - ns v cc < 4.5 v 37 when rdy is input when rdy is released 2 cycles t rdyi 0.5v cc mclk original moex mwex mrdy mclk extended moex mwex mrdy over 2cycles t rdyi
document number: 002 - 05661 rev. *d page 91 of 131 mb9b520ta series 12.4.9 base timer input timing timer input timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh , t tiwl tioan/tiobn (when using as eck, tin) - 2 t cycp - ns trigger input timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh , t trgl tioan/tiobn (when using as tgin) - 2 t cycp - ns note: ? t cycp indicates the apb bus clock cycle time. about the apb bus number which the base timer is c onnected to, see 8 . block diagram in this data sheet. eck tin tgin t tiwh v ihs v ihs v ils v ils t tiw l t trgh v ihs v ihs v ils v ils t trg l
document number: 002 - 05661 rev. *d page 92 of 131 mb9b520ta series 12.4.10 csio/uart timing csio (spi = 0, scinv = 0) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sck x master mode 4t cycp - 4t cycp - ns sck sot delay time t slovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivshi sckx , sinx 50 - 30 - ns sck sin hold time t shixi sckx , sinx 0 - 0 - ns serial clock "l" pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t slove sckx , sotx - 50 - 3 3 ns sin sck setup time t ivshe sckx , sinx 10 - 10 - ns sck sin hold time t shixe sckx , sinx 20 - 20 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. ? about the apb bus number which multi - function serial is connected to, see " 8 . block diagram " in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? when the external load capacitance c l = 30pf.
document number: 002 - 05661 rev. *d page 93 of 131 mb9b520ta series master mode slave mode sck sot sin sck sot sin t scyc v oh v oh v ol v ol v ol v ih v il v ih v il t slovi t ivshi t shixi t slsh t shsl v ih t f tr v ih v oh v ih v il v il v ol v ih v il v ih v il t slove t ivshe t shixe
document number: 002 - 05661 rev. *d page 94 of 131 mb9b520ta series csio (spi = 0, scinv = 1) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max b aud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4t cycp - 4t cycp - ns sck sot delay time t shovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivsli sckx , sinx 50 - 30 - ns sck sin hold time t slixi sckx , sinx 0 - 0 - ns serial clock "l" pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t shove sckx , sotx - 50 - 3 3 ns sin sck setup time t ivsle sckx , sinx 10 - 10 - ns sck sin hold time t slixe sckx , sinx 20 - 20 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. ? about the apb bus number which multi - functi on serial is connected to, see 8 . block diagram in this datasheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? when the external load ca pacitance c l = 30 pf.
document number: 002 - 05661 rev. *d page 95 of 131 mb9b520ta series master mode slave mode sck sot sin sck sot sin t scyc v oh v oh v oh v ol v ol v ih v il v ih v il t shovi t ivsli t slixi t shsl t slsh v ih tf tr v ih v oh v il v il v il v ol v ih v il v ih v il t shove t ivsle t slixe
document number: 002 - 05661 rev. *d page 96 of 131 mb9b520ta series csio (spi = 1, scinv = 0) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4t cycp - 4t cycp - ns sck sot delay time t shovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivsli sckx , sinx 50 - 30 - ns sck sin hold time t slixi sckx , sinx 0 - 0 - ns sot sck delay time t sovli sckx , sotx 2t cycp - 30 - 2t cycp - 30 - ns serial clock "l" pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t shove sckx , s ot x - 50 - 3 3 ns sin sck setup time t ivsle sckx , sinx 10 - 10 - ns sck sin hold time t slixe sckx , sinx 20 - 20 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes : ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. ? about the apb bus number which multi - function serial is connected to, see 8 . block diagram in this data sheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sotx_1 is not guaranteed. ? when the external load capacitance c l = 30 pf.
document number: 002 - 05661 rev. *d page 97 of 131 mb9b520ta series master mode slave mode *: changes when writing to tdr register sck sot sin sck sot sin t sovli t scyc t shovi v ol v ol v oh v oh v ol v oh v ol v ih v il v ih v il t ivsli t slixi tf tr t slsh t shsl t shove v il v il v ih v ih v ih v oh * v ol v oh v ol v ih v il v ih v il t ivsle t slixe
document number: 002 - 05661 rev. *d page 98 of 131 mb9b520ta series csio (spi = 1, scinv = 1) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions v cc < 4.5 v v cc 4.5 v unit min max min max baud rate - - - - 8 - 8 mbps serial clock cycle time t scyc sckx master mode 4t cycp - 4t cycp - ns sck sot delay time t slovi sckx , sotx - 30 + 30 - 20 + 20 ns sin sck setup time t ivshi sckx , sinx 50 - 30 - ns sck sin hold time t shixi sckx , sinx 0 - 0 - ns sot sck delay time t sovhi sckx , sotx 2t cycp - 30 - 2t cycp - 30 - ns serial clock "l" pulse width t slsh sckx slave mode 2t cycp - 10 - 2t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t slove sckx , s ot x - 50 - 3 3 ns sin sck setup time t ivshe sckx , sinx 10 - 10 - ns sck sin hold time t shixe sckx , sinx 20 - 20 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. ? about the apb bus number which multi - function serial is connected to, see 8 . block diagram in this datasheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sckx_0 and sot x_1 is not guaranteed. ? when the external load capacitance c l = 30 pf.
document number: 002 - 05661 rev. *d page 99 of 131 mb9b520ta series master mode slave mode uart external clock input (ext = 1) (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol conditions value unit remarks min max serial clock " l" pulse width t slsh c l = 30 pf t cycp + 10 - ns serial clock " h" pulse width t shsl t cycp + 10 - ns sck falling time tf - 5 ns sck rising time tr - 5 ns t shsl v i l v i l v i l v ih v ih v ih tr tf t slsh s ck sck sot sin sck sot sin t scyc t slovi v ol v oh v oh v oh v ol v oh v ol v ih v il v ih v il t ivshi t shixi t sovhi t s h s l t r t s l s h t s l o v e v i l v i l v i l v i h v i h v i h v o h v o l v o h v o l v i h v i l v i h v i l t i v s h e t s h i x e t f
document number: 002 - 05661 rev. *d page 100 of 131 mb9b520ta series 12.4.11 external input timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions value unit remarks min max input pulse width t inh , t inl adtg - 2 t cycp * 1 - n s a/d converter trigger input frckx free - run timer input clock icxx input capture dttixx - 2 t cycp * 1 - ns waveform generator int xx *2 2 t cycp + 100 * 1 - ns external interrupt , nmi *3 500 - ns wkupx *4 500 - ns deep standby wake up *1: t cycp indicates the apb bus clock cycle time. about the apb bus number which the a/d converter, multi - function timer, external i nterrupt are connected to, see 8 . block diagram in this data sheet. *2: when in run mode, in sleep mode. *3: when in stop mode, in timer mode. *4: when in deep standby rtc mode, in deep standby stop mode.
document number: 002 - 05661 rev. *d page 101 of 131 mb9b520ta series 12.4.12 quadrature position/revolution counter timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol conditions value unit min max ain pin "h" width t ahl - 2 t cycp * - ns ain pin "l" width t all - bin pin "h" width t bhl - bin pin "l" width t bll - t ime from ain pin "h" level to bin rise t aubu pc_mode2 or pc_ m ode3 t ime from bin pin "h" level to ain fall t buad pc_mode2 or pc_mode3 t ime from ain pin "l" level to bin fall t adbd pc_mode2 or pc_mode3 t ime from bin pin "l" level to ain rise t bdau pc_mode2 or pc_mode3 t ime from bin pin "h" level to ain rise t buau pc_mode2 or pc_mode3 t ime from ain pin "h" level to bin fall t aubd pc_mode2 or pc_mode3 t ime from bin pin "l" level to ain fall t bdad pc_mode2 or pc_mode3 t ime from ain pin "l" level to bin rise t adbu pc_mode2 or pc_mode3 zin pin "h" width t zhl qcr:cgsc="0" zin pin "l" width t zll qcr:cgsc="0" time from determined zin level to ain/bin rise and fall t zabe qcr:cgsc="1" time from ain/bin rise and fall time to determined zin level t abez qcr:cgsc="1" *: t cycp indicates the apb bus clock cycle time. about the apb bus number which the quadrature position/revolutio n counter is connected to, see 8 . block diagram in this data sheet. ain bin t aubu t buad t adbd t bdau t ahl t all t bhl t bll
document number: 002 - 05661 rev. *d page 102 of 131 mb9b520ta series zin zin ain/bin bin t buau t aubd t bdad t adbu t bhl t bll t ahl t all ain
document number: 002 - 05661 rev. *d page 103 of 131 mb9b520ta series 12.4.13 i 2 c timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol conditions standard - mode fast - mode unit remarks v max min max scl clock frequency f scl c l = 30 pf, r = (vp/i ol ) * 1 0 100 0 400 khz (repeated) start condition hold time sda scl t hdsta 4.0 - 0.6 - s sclclock "l" width t low 4.7 - 1.3 - s sclclock "h" width t high 4.0 - 0.6 - s (repeated) start condition setup time scl sda t susta 4.7 - 0.6 - s data hold time scl sda t hddat 0 3.45* 2 0 0.9* 3 s data setup time sda scl t sudat 250 - 100 - ns stop condition setup time scl sda t susto 4.0 - 0.6 - s bus free time between "stop condition" and "start condition" t buf 4.7 - 1.3 - s noise filter t sp - 2 t cycp * 4 - 2 t cycp * 4 - ns *1 : r and c l represent the pull - up resistor and load capacitance of the scl and sda lines, respectively. vp indicates the power supply voltage of the pull - up resistor and i ol indicates v ol guaranteed current. *2: the maximum t hddat must satisfy that it does not extend at least "l" period (t low ) of device's scl signal. *3: fast - mode i 2 c bus device can be used on s tandard - mode i 2 c bus system as long as the device satisfies the requirement of "t sudat 250 ns". *4: t cycp is the apb bus clock cycle time. about the apb bus number that i 2 c is c onnected to, see " 8 . block diagram " in this data sheet. to use standard - mode , set the apb bus clock at 2 mhz or more. to use fast - mode , set the apb bus clock at 8 mhz or more. sda s cl
document number: 002 - 05661 rev. *d page 104 of 131 mb9b520ta series 12.4.14 etm timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions value unit remarks min max data hold t etmh traceclk , traced [ 3 : 0 ] v cc 4.5 v 2 1 0 ns v cc < 4.5 v 2 15 traceclk frequency 1/ t trace traceclk v cc 4.5 v - 40 mhz v cc < 4.5 v - 20 mhz traceclk clock cycle t trace v cc 4.5 v 25 - ns v cc < 4.5 v 50 - ns note: ? when the external load capacitance c l = 30 pf. hclk traceclk traced[3:0]
document number: 002 - 05661 rev. *d page 105 of 131 mb9b520ta series 12.4.15 jtag timing (v cc = 2.7v to 5.5v, v ss = 0v, t a = - 40 c to + 105 c ) parameter symbol pin name conditions value unit remarks min max tms , tdi setup time t jtags tck , tms , tdi v cc 4.5 v 15 - ns v cc < 4.5 v tms , tdi hold time t jtagh tck , tms , tdi v cc 4.5 v 15 - ns v cc < 4.5 v tdo delay time t jtagd tck , tdo v cc 4.5 v - 25 ns v cc < 4.5 v - 45 note: ? when the external load capacitance c l = 30 pf. tck tms/ tdi tdo
document number: 002 - 05661 rev. *d page 106 of 131 mb9b520ta series 12.5 12 - bit a/d converter electrical characteristics for the a/d converter (v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name value unit remarks min typ max resolution - - - - 12 bit integral nonl inearity - - - 1.5 4.5 lsb avrh = 2.7 v to 5.5 v differential non linearity - - - 2.2 2.5 lsb zero transition voltage v zt an xx - 6 15 mv full - scale transition voltage v fst an xx - avrh 5 avrh 15 mv conversion time - - 1 .0 * 1 - - s sampling time* 2 ts - 0.3 - 10 s compare clock cycle* 3 tcck - 50 - 1000 ns state transition time to operation permission tstt - - - 1.0 s analog input capacity c ain - - - 9. 5 pf analog input resistor r ain - - - 1.62 k av cc 4.5 v 2.35 av cc < 4.5 v interchannel disparity - - - - 4 lsb analog port input leak current - an xx - - 5 a analog input voltage - an xx av rl - avrh v reference voltage - avrh 2.7 - av cc v - avrl av ss - av ss v *1: the conversion time is the value of sampling time (ts) + compare time (tc). the condition of the minimum conversion time is when the value of sampling time: 3 0 0 ns , the value of compare time: 7 0 0 n s (av cc 4.5 v). ensure that it satisfies the value of the sampling time (ts) and compare clock cycle (tcck). for setting of the sampling time and compare clock cycle, see " c hapter 1 - 1 : a/d converter " in " fm3 family peripheral manual analog macro part ". the register setting of the a/d converter are reflected in the operation according to the apb bus clock timing. the sampling clock and compare clock is generated from the base clock (hclk). about the apb bus number which the a/d conv erter is connected to, see " 8 . block diagram " in this data sheet. *2: a necessary sampling time changes by external impedance. ensure that it sets the sampling time to satisfy ( equation 1 ). *3: the compare time ( tc ) is the value of ( equation 2).
document number: 002 - 05661 rev. *d page 107 of 131 mb9b520ta series (equation 1) t s ( r ain + r ext ) c ain 9 ts : sampling time r ain : i nput resistor of a/d = 1.62 k ch.0 to ch.7 at 4.5 v < av cc < 5.5 v i nput resistor of a/d = 1.58 k ch.8 to ch.15 at 4.5 v < av cc < 5.5 v i nput resistor of a/d = 1. 56 k ch.16 to ch.23 at 4.5 v < av cc < 5.5 v i nput resistor of a/d = 2.35 k ch.0 to ch.7 at 2.7 v < av cc < 4.5 v i nput resistor of a/d = 2.3 k ch.8 to ch.15 at 2.7 v < av cc < 4.5 v i nput resistor of a/d = 2. 25 k ch.16 to ch.23 at 2.7 v < av cc < 4.5 v c ain : i nput capacity of a/d = 9.5 pf at 2.7 v < av cc < 5.5 v r ext : output impedance of external circuit ( equation 2 ) t c = t cck 14 tc : compare time tcck : compare clock cycle r ain c ain analog signal source r ext an xx analog input pin c omparator
document number: 002 - 05661 rev. *d page 108 of 131 mb9b520ta series definition of 12 - bit a/d converter terms ? resolution : analog variation that is recognized by an a/d converter. ? integral nonlinearity : deviation of the line between the zero - transition point (0b000000000000 0b000000000001) and the full - scale transition point ( 0b111111111110 0b111111111111) from the actual conversion characteristics. ? differential non linearity : deviation from the ideal value of the input voltage that is required to change the output code by 1 lsb. integral nonlinearity of digital output n = v nt - {1lsb (n - 1) + v z t } [lsb] 1lsb differential nonlinearity of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst C v z t 4094 n: a/d converter digital output value. v z t : voltage at whi ch the digital output ch anges from 0x000 to 0x001. v fst : voltage at whi ch the digital output ch anges from 0xffe to 0xfff. v nt : voltage at whi ch the digital output ch anges from 0x(n ? 1) to 0xn. integral nonl inearity differential non linearity digital output digital output actual conversion characteristics actual conversion characteristics ideal characteristics (actually - measured value) actual conversion characteristics actual conversion characteristics (actually - measured value) (actually - measured value) ideal characteristics (actually - measured value) analog input analog input (actually - measured value) 0x001 0x002 0x003 0x004 0x f fd 0x f fe 0x f ff avrl avrh avrl avrh 0x(n - 2) 0x(n - 1) 0x(n+1) 0xn {1 lsb(n - 1) + v zt } v nt v fst v zt v nt v (n+1)t
document number: 002 - 05661 rev. *d page 109 of 131 mb9b520ta series 12.6 10 - bit d/a converter electrical characteristics for the d/a converter (v cc = av cc = 2.7v to 5.5v, v ss = av ss = avrl = 0v, t a = - 40 c to + 105 c) parameter symbol pin name value unit remarks min typ max resolution - dax - - 10 bit conversion time tc20 0. 4 7 0.5 8 0.69 s load 20 pf tc100 2.37 2. 90 3.4 3 s load 100 pf integral nonl inearity * 1 inl - 4.0 - + 4.0 lsb differential non linearity * 1, * 2 dnl - 0.9 - + 0.9 lsb output voltage offset v off - - 10.0 mv code is 0x000 - 20 .0 - + 5. 4 mv code is 0x3ff analog output impedance r o 3.10 3. 8 0 4.5 0 k d/a operation 2.0 - - m d/a stop output undefined period t r - - 70 ns *1: no - load *2: generates the max current by the code about 0x200
document number: 002 - 05661 rev. *d page 110 of 131 mb9b520ta series 12.7 usb characteristics (v cc = 2.7v to 5.5v, usbv cc = 3.0v to 3.6v, v ss = 0v, t a = - 40 c to + 105 c) parameter symbol pin name conditions value unit remarks m in m ax input charact - eristics input "h" level voltage v ih udp0, udm0 - 2.0 usbv cc + 0.3 v *1 input "l" level voltage v il - v ss - 0.3 0.8 v *1 differential input sensitivity v di - 0.2 - v *2 different common mode range v cm - 0.8 2.5 v *2 output charact - eristics output "h" level voltage v oh external pull - down resistor = 15 k 2.8 3.6 v *3 output "l" level voltage v ol external pull - up resistor = 1.5 k 0.0 0.3 v *3 crossover voltage v crs - 1.3 2.0 v *4 rising time t fr full - speed 4 20 ns *5 falling time t ff full - speed 4 20 ns *5 rising/falling time matching t frfm full - speed 90 111.11 % *5 output impedance z drv full - speed 28 44 *6 rising time t lr low - speed 75 300 ns *7 falling time t lf low - speed 75 300 ns *7 rising/falling time matching t lrfm low - speed 80 125 % *7 *1: the switching threshold voltage of the single - end - receiver of us b i/o buffer is set as within v il (max) = 0.8 v, v ih (min) = 2.0 v (ttl input standard). there are some hysteresis to lower noise sensitivity. *2: u se the differential - receiver to receive the usb differential data signal. the differential - receiver has 200 mv of differential input sensitivity when the differential data input is within 0.8 v to 2.5 v to the local ground reference level. the voltage range above is said to be the common mode input voltage range. common mode input voltage [v] minimum differential input sensitivity [v]
document number: 002 - 05661 rev. *d page 111 of 131 mb9b520ta series *3: the output drive capability of the driver is below 0.3 v at low - state (v ol ) (to 3.6 v and 1.5 k load), and 2.8 v or above (to ground and 15 k load) at high - state (v oh ). *4: the cross voltage of the external differential output signal (d + /d ? ) of usb i/o buffer is within 1.3 v to 2.0 v. *5: they indicate rising time (trise) and falling time (tfall) of the full - speed differential data signal. they are defined by the time between 10% and 90% of the output signal voltage. for full - speed buffer, tr/tf ratio is regulated as within 10% to minimize rfi emission. v crs specified range rising time falling time
document number: 002 - 05661 rev. *d page 112 of 131 mb9b520ta series *6: usb full - speed connection is performed via twist pair cable shield with 90 15% characteristic impedance (differential mode). usb standard defines that output impedance of usb driver must be in range from 28 to 44 . so, discrete series resistor (rs) addition is defined in order to satisfy the above definition and keep balance. when using this usb i/o, use it with 25 to 30 (recommendation value 27 ) series resistor rs . rs series resistor 25 to 30 series resistor of 27 (recommendation value) must be added. and, use "resistance with an uncertainty of 5% by e24 sequence". *7: they indicate rising time (trise) and falling time (tfall) of the low - speed differential data signal. they are defined by the time between 10% and 90% of the output signal voltage. see low - speed load (compliance load) for conditions of the external load. rising time falling time mount it as external resistor . 28 to 44 equiv. imped. 28 to 44 equiv. imped.
document number: 002 - 05661 rev. *d page 113 of 131 mb9b520ta series low - speed load (upstream port load) - reference 1 low - speed load (downstream port load) - reference 2 low - speed load (compliance load) c l = 50pf to 150pf c l = 50pf to 150pf c l = 200pf to 600pf c l = 200pf to 600pf c l = 200pf to 450pf c l = 200pf to 450pf
document number: 002 - 05661 rev. *d page 114 of 131 mb9b520ta series 12.8 low - voltage detection characteristics 12.8.1 low - voltage detection reset ( t a = - 40 c to + 105 c) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhr * 1 = 0 0000 2.25 2.45 2.65 v when voltage drops released voltage vdh 2.30 2.50 2.70 v when voltage rises detected voltage vdl svhr * 1 = 0 0001 2.39 2.60 2.81 v when voltage drops released voltage vdh same as svhr = 0000 0 value v when voltage rises detected voltage vdl svhr * 1 = 0 0010 2.48 2.70 2.92 v when voltage drops released voltage vdh same as svhr = 0000 0 value v when voltage rises detected voltage vdl svhr * 1 = 0 0011 2.58 2.80 3.02 v when voltage drops released voltage vdh same as svhr = 0000 0 value v when voltage rises detected voltage vdl svhr * 1 = 0 0100 2.76 3.00 3.24 v when voltage drops released voltage vdh same as svhr = 0000 0 value v when voltage rises detected voltage vdl svhr * 1 = 0 0101 2.94 3.20 3.46 v when voltage drops released voltage vdh same as svhr = 0000 0 value v when voltage rises detected voltage vdl svhr * 1 = 0 0110 3.31 3.60 3.89 v when voltage drops released voltage vdh same as svhr = 0000 0 value v when voltage rises detected voltage vdl svhr * 1 = 0 0111 3.40 3.70 4.00 v when voltage drops released voltage vdh same as svhr = 0000 0 value v when voltage rises detected voltage vdl svhr * 1 = 0 1000 3.68 4.00 4.32 v when voltage drops released voltage vdh same as svhr = 0000 0 value v when voltage rises detected voltage vdl svhr * 1 = 0 1001 3.77 4.10 4.43 v when voltage drops released voltage vdh same as svhr = 0000 0 value v when voltage rises detected voltage vdl svhr * 1 = 0 1010 3.86 4.20 4.54 v when voltage drops released voltage vdh same as svhr = 0000 0 value v when voltage rises lvd stabilization wait time t lvdw - - - 6432 t cycp * 2 s lvd detection delay time t lvd dl - - - 200 s *1: the svhr bit of low - v oltage detection voltage control register (lvd_ctl ) is initialized to "00000" by low - voltage d etection r eset. *2: t cycp indicates the apb2 bus clock cycle time.
document number: 002 - 05661 rev. *d page 115 of 131 mb9b520ta series 12.8.2 interrupt of low - voltage detection ( t a = - 40 c to + 105 c) parameter symbol conditions value unit remarks min typ max detected voltage vdl svhi = 0 0011 2.58 2.80 3.02 v when voltage drops released voltage vdh 2.67 2.90 3.13 v when voltage rises detected voltage vdl svhi = 0 0100 2.76 3.00 3.24 v when voltage drops released voltage vdh 2.85 3.10 3.35 v when voltage rises detected voltage vdl svhi = 0 0101 2.94 3.20 3.46 v when voltage drops released voltage vdh 3.04 3.30 3.56 v when voltage rises detected voltage vdl svhi = 0 0110 3.31 3.60 3.89 v when voltage drops released voltage vdh 3.40 3.70 4.00 v when voltage rises detected voltage vdl svhi = 0 0111 3.40 3 . 70 4.00 v when voltage drops released voltage vdh 3.50 3 . 8 0 4.10 v when voltage rises detected voltage vdl svhi = 0 1000 3.68 4 . 00 4.32 v when voltage drops released voltage vdh 3.77 4.10 4.43 v when voltage rises detected voltage vdl svhi = 0 1001 3.77 4 . 10 4.43 v when voltage drops released voltage vdh 3.86 4.20 4.54 v when voltage rises detected voltage vdl svhi = 0 1010 3.86 4 . 20 4.54 v when voltage drops released voltage vdh 3.96 4. 3 0 4. 64 v when voltage rises lvd stabilization wait time t lvdw - - - 6432 t cycp * s lvd detection delay time t lvd dl - - - 200 s *: t cycp indicates the apb2 bus clock cycle time.
document number: 002 - 05661 rev. *d page 116 of 131 mb9b520ta series 12.9 flash memory write/erase characteristics 12.9.1 write / erase time ( v cc = 2.7v to 5.5v , t a = - 40 c to + 105 c ) parameter value unit remarks typ max sector erase time large sector 1.1 2.7 s includ es write time prior to internal erase small sector 0. 3 0.9 half word (16 - bit) write time 20 317 s not including system - level overhead time ch ip erase time 31 79 s includes write time prior to internal erase *: the typical value is immediately after shipment , the maximum value is guarantee value under 10,000 cycle of erase/write . 12.9.2 write cycles and data hold time erase/write cycles (cycle) data hold time (year ) remarks 1 , 000 20* 10 , 000 10* *: at average + 85 c
document number: 002 - 05661 rev. *d page 117 of 131 mb9b520ta series 12.10 return time from low - power consumption mode 12.10.1 return factor: interrupt/wkup the return time from low - power consumption mode is indicated as follows. it is from receiving the return factor to starting the program operation. return count time ( v cc = 2.7v to 5.5v , t a = - 40 c to + 105 c ) parameter symbol value unit remarks typ max* sleep mode ticnt t cycc n s high - speed cr timer mode , main timer mode , pll timer mode 43 83 s low - speed cr timer mode 310 620 s sub timer mode 534 724 s rtc mode , stop mode 278 479 s deep standby rtc mode, deep standby stop mode 298 543 s when ram is off 288 523 s when ram is o n *: the maximum value depends on the accuracy of built - in cr. operation example of return from low - power consumption mode (by external interrupt*) *: external interrupt is set to detecting fall edge. e x t . i n t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u
document number: 002 - 05661 rev. *d page 118 of 131 mb9b520ta series operation example of return from low - power consumption mode (by internal resource interrupt*) *: internal resource interrupt is not included in return factor by the kind of low - power consumption mode. notes: ? the return factor is different in each low - power consumption modes. see " chapter 6: low power consumption mode" and "operations of standby modes" in fm3 family peripheral manual about the return factor from low - power consumption mode ? when interrupt recoveries, the operation mode that cpu recoveries depends on the state before the low - power consumption mode transiti on. see " chapter 6: low power consumption mode" in "fm3 family peripheral manual". i n t e r n a l r e s o u r c e i n t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u
document number: 002 - 05661 rev. *d page 119 of 131 mb9b520ta series 12.10.2 return factor: reset the return time from low - power consumption mode is indicated as follows. it is from releasing reset to starting the program operation. return count time ( v cc = 2.7v to 5.5v , t a = - 40 c to + 105 c ) parameter symbol value unit remarks typ max* sleep mode trcnt 149 264 s high - speed cr timer mode , main timer mode , pll timer mode 149 264 s low - speed cr timer mode 318 603 s sub timer mode 308 583 s rtc/stop mode 248 443 s deep standby rtc mode, deep standby stop mode 298 543 s when ram is off 288 523 s when ram is o n *: the maximum value depends on the accuracy of built - in cr. operation example of return from low - power consumption mode (by initx) i n i t x t r c n t i n t e r n a l r s t c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e
document number: 002 - 05661 rev. *d page 120 of 131 mb9b520ta series operation example of return from low power consumption mode (by internal resource reset*) *: internal resource reset is not included in return factor by the kind of low - power consumption mode. notes: ? the return factor is different in each low - power consumption modes. see " chapter 6: low power consumption mode" and "operations of standby modes" in fm3 family peripheral man ual. ? when interrupt recoveries, the operation mode that cpu recoveries depend on the state before the low - power consumption mode transition. see " chapter 6: low power consumption mode" in "fm3 family peripheral manual" the time during the power - on reset/lo w - voltage detection reset is excluded. see 12.4.7 . power - on reset timing in 12.4 . ac characteristics in 12 . electrical characteristics " for the detail on the time during the power - on reset/low - voltage detection reset. ? when in recovery from reset, cpu ch anges to the high - speed cr run mode. when using the main clock or the pll clock, it is necessary to add the main clock oscillation stabilization wait time or the main pll clock stabilization wait time. ? the internal resource reset means the watchdog reset a nd the csv reset. i n t e r n a l r e s o u r c e r s t t r c n t i n t e r n a l r s t c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e
document number: 002 - 05661 rev. *d page 121 of 131 mb9b520ta series 13. ordering information part number on - chip flash memory on - chip sram package packing mb9bf5 28sa pmc - g k7 e 2 main: 1 mbyte work: 64 kbyte 160 kbyte plastic ? lqfp , 1 44 - pin (0.5 mm pitch ) ( lqs 144) tray mb9bf5 29sa pmc - g k7 e 2 main: 1.5 mbyte work: 64 kbyte 192 kbyte mb9bf5 28tapmc - g k7 e 2 main: 1 mbyte work: 64 kbyte 160 kbyte plastic ? lqfp , 176 - pin (0.5 mm pitch ) ( lqp 176 ) mb9bf5 29tapmc - g k7 e 2 main: 1.5 mbyte work: 64 kbyte 192 kbyte mb9bf5 28ta bgl - g k7 e1 main: 1 mbyte work: 64 kbyte 160 kbyte plastic ? fbga , 192 - pin (0. 8 mm pitch ) ( lbe 192 ) mb9bf5 29ta bgl - g k7 e1 main: 1.5 mbyte work: 64 kbyte 192 kbyte
document number: 002 - 05661 rev. *d page 122 of 131 mb9b520ta series 14. package dimensions package type package code lqfp 176 lqp176 002 - 1 5 150 ** d i mensi o n s s ymb o l m i n . n o m . max. a 1 . 7 0 a1 0 . 0 5 0 . 1 5 b 0 . 1 7 0 . 2 2 0 . 2 7 c 0 . 0 9 0 . 2 0 d 2 6 . 0 0 b sc d 1 2 4 . 0 0 b sc e 0 . 5 0 bs c e e1 l 0 . 4 5 0 . 6 0 0 . 7 5 l 1 2 6 . 0 0 b sc 2 4 . 0 0 b sc 0 . 3 0 0 . 5 0 0 . 7 0 0 8 1 17 6 e d 1 d e e 1 3 3 0. 0 8 c a - b d b 0. 1 0 c a - b d 8 7 5 2 2 0. 0 8 c a a ' s ea t in g p l an e 4 5 7 4 5 7 a a 1 0. 2 5 1 0 l 1 l b s e c t i o n a - a ' c 9 6 0. 2 0 c a - b d s i de view top view b ottom view 1 17 6 4 4 4 5 8 8 8 9 13 2 13 3 4 4 4 5 8 8 2 3 1 9 8 13 3 package ou t line, 1 76 le a d l q f p 24.0x24.0x1.7 mm lq p 176 r ev * *
document number: 002 - 05661 rev. *d page 123 of 131 mb9b520ta series package type package code lqfp 144 lqs144 002 - 1 3015 * a d i m e n s i o n s sym b o l m i n . n om . m ax . a 1 . 7 0 a 1 0 . 0 5 0 . 1 5 b 0 . 1 7 0 . 2 7 c 0 . 0 9 0 . 2 0 d 22.00 bsc d 1 20.00 bsc e 0.50 bsc e e 1 l 0 . 4 5 0 . 6 0 0 . 7 5 l1 0 . 3 0 0 . 5 0 0 . 7 0 22.00 bsc 20.00 bsc 0 . 2 2 1 14 4 d 1 d e e e 1 0.2 0 c a - b d 0.0 8 c a - b d b 0.1 0 c a - b d a a ' s e a t i n g plan e 0.0 8 c a a 1 0 . 2 5 10 l 1 l b se c t ion a-a ' c 9 4 5 7 3 3 8 7 5 2 2 4 5 7 6 14 4 d 1 d e e 1 4 5 7 3 4 5 7 3 6 3 7 7 2 7 3 10 8 10 9 3 7 7 2 10 9 3 6 1 8 0 1 3 7 s ide vie w t o p v i e w b o tt o m vie w package ou t line, 1 44 le a d l q f p 20 . 0x20 . 0x1 . 7 m m lq s144 r ev * a
document number: 002 - 05661 rev. *d page 124 of 131 mb9b520ta series package type package code bga 192 lbe192 002 - 1 3493 * a
document number: 002 - 05661 rev. *d page 125 of 131 mb9b520ta series 15. errata this chapter describes the errata for mb9b 5 20t series . details include errata trigger conditions, scope of impact, available workaround, and silicon revision applicability. contact your local cypress sales representative if you have questions. 15.1 part numbers affected part number initial revision mb9bf 5 28tpmc - ge2, mb9bf 5 29tpmc - ge2, mb9bf 5 28tbgl - ge1, mb9bf 5 29tbgl - ge1, mb9bf 5 28spmc - ge2, mb9bf 5 29spmc - ge2 , mb9bf 5 28tpmc - g k7 e2, mb9bf 5 29tpmc - g k7 e2, mb9bf 5 28tbgl - g k7 e1, mb9bf 5 29tbgl - g k7 e1, mb9bf 5 28spmc - g k7 e2, mb9bf 5 29spmc - g k7 e2 15.2 qualification status product status: in production ? qual. 15.3 errata summary this table defines the errata applicability to available devices. items p art number silicon revision fix status [ 1 ] hdmi - cec polling message issue refer to 15.1 initial rev. fixed in rev. a 15.4 errata detail 15.4.1 hdmi - cec polling message issue ? problem definition error#1) while mcu sends a polling message, it always returns a nack to a message coming to the mcu from another node. error#2) mcu always waits for 7 - bit signal free on cec line before it drives the line even when the last line initiator was another node. ? parameters affected n/a ? trigger condition(s) this error always happens. ? scope of impact mcu does not reply properly to another node. ? workaround the software workaround is applied to error #1. 1. store 0x0 to sfree register. 2. monitor cec line with gpio and wait until 1 lasts for the signal free time. 3. store frame data to txdata register and store 0x0f to rcadr1 or rcadr2 register. it sends a message after 3~4 clocks of 32.768 khz clock when txdata is store d 0x0f. if the device receives a frame from another node within 2~3 clocks after storing txdata, the bus error occurs and if the devi ce receives a frame from another node within 3~4 clocks after storing txdata, the arbitration lost occurs. in these cases:
document number: 002 - 05661 rev. *d page 126 of 131 mb9b520ta series 4 - a - 1 . set rcadr1 or rcadr2 to former value from 0x0f to reply ack 4 - a - 2. return back to step 2 above if the device receives a frame from another node within 1~2 clocks after storing txdata, take these steps. 4 - b - 1. monitor cec line with gpio after 50us fr om storing txdata 4 - b - 2. set txen to 1 - > 0 - > 1 immediately when gpio finds state low on the cec line 4 - b - 3. set rcadr1 or rcadr2 to former value from 0x0f to reply ack 4 - b - 4. return back to step 2 above for error #2, there is no software workaround, but signal free time of fixed 7 - bit does not violate hdmi - cec specification. the specification says signal free time must be more than and equals to 5 - bit. ? fix status this issue was fixed in rev. a .
document number: 002 - 05661 rev. *d page 127 of 131 mb9b520ta series 16. major changes spans ion publication number: ds706 - 000 60 pa ge section change results revision 0.1 - - initial release revision 0.2 - - company name and layout design change revision 1.0 - - p reliminary full production 2 features external bus interface ad ded the descriptions as follows maximum area size : up to 256 mbytes 4 features a/d converter ? corrected conversion time 5 features multi - function timer ? corrected the channel count of "a/d activation compare" 8 product lineup function added the footnote 64 handling devices power supply pins ? added the description 66 block diagram ? corrected the figure 67 memory map ? memory map (1) ? corrected the address of external device area 77 electrical characteristics 1. absolute maximum ratings added the item of input voltage 79 2. recommended operating conditions added the footnote 80 - 82 3. dc characteristics (1) current rating corrected the condition corrected the value corrected the remarks added the footnote 84 (2) pin characteristics added the item of input leak current 89 4. ac characteristics (6) power - on reset timing revised the values of time until releasing power - on reset corrected the figure corrected the glossary 108 (9) csio timing synchronous serial (spi=1, scinv=1) corrected the figure of ms bit=1 external clock (ext=1): asynchronous only ? corrected the figure 115 5. 12 - bit a/d converter electrical characteristics for the a/d converter corrected the pins name an00 - an23 anxx corrected the min vale of conversion time corrected the min vale of sampling time corrected the min value of compare clock cycle corrected the state transit on time to operation permission corrected the footnote 125 9. electrical characteristics for the a/d converter (1) write / erase time revised the values of tbd 126 10. return time from low - power consumption mode (1) return factor: interrupt/wkup return count time revised the values of tbd 128 (2) return f actor: reset return count time revised the values of tbd revision 2.0 - - changed the series name. mb9b520t series - > mb9b520ta series - - changed the product name as follows. mb9bf528sa, mb9bf529sa, mb9bf528ta, mb9bf529ta 2 features usb interface added the description of pll for usb 42 to 49 l ist of p in f unctions list of pin functions added lin to the description of sotxx
document number: 002 - 05661 rev. *d page 128 of 131 mb9b520ta series pa ge section change results 56, 57 i/o circuit type added about +b input 68 memory map memory map(2) added the summary of flash memory sector 77, 78 electrical characteristics 1. absolute maximum ratings added the clamp maximum current added about +b input 80, 81 electrical characteristics 3. dc characteristics (1) current rating changed the expression of condition added main timer mode current 88 electrical characteristics 4. ac characteristics (4 - 1) operating conditions of main and usb pll (4 - 2) operating conditions of ma in pll added the figure of main pll connection and usb pll connection 101 to 108 electrical characteristics 4. ac characteristics (7) csio/uart timing modified from uart timing to csio/uart timing changed from internal shift clock operation to master mode changed from external shift clock operation to slave mode 115 electrical characteristics 5. 12bit a/d converter added the typical value of integral nonlinearity, differential nonlinearity, zero transition voltage and full - scale transition voltage 130 ordering information change to full part number note : please see document history about later revised information.
document number: 002 - 05661 rev. *d page 129 of 131 mb9b520ta series document history document title : mb9b520ta series 32 - bit arm? cortex? - m3, fm3 microcontroller document number : 002 - 05661 revision ecn orig. of change submission date description of change ** C toyo 0 1/30/2015 migrated to cypress and assigned document number 002 - 05661 . no change to document contents or format. *a 5204832 toyo 0 4 / 0 6 /201 6 updated to cypress format. *b 5653479 nos u 0 3 / 1 0 /201 7 updated cypress logo corrected the package code s the following chapters as the table below. 2. packages 3. pin assignment 13. ordering information 14. package dimensions before after fpt - 1 44 p - m 08 lq s 1 44 fpt - 176 p - m 07 lq p 1 76 bga - 1 92 p - m0 6 lb e 1 9 2 corrected the following statement usb function ? usb device in chapter. features ( page 1 ) 1. product lineup ( page 7 ) 4. list of pin functions ( page 42 ) 8. block diagram ( page 56 ) m odified rtc description in chapter featur es before the interrupt function with specifying date and time (year/month/day/hour/minute /second/a day of the week .) is available. after the interrupt function with specifying date and time (year/month/day/hour/minute.) is available. corrected a word j - tag to jtag in 4. list of pin functions ( page 28 ) added a note of tap controller in 4. list of pin functions ( page 44 ) corrected sector size of memory map (2) in 10. memory map . rom1_sa8_15( 8 kbx8) ? rom1_sa8_15(64kbx8) replaced a word ta to t a in the following chapters. 12.2. recommended operating conditions 12.3. dc characteristics 12.4. ac characteristics 12.5. 12 - bit a/d converter 12.6. 10 - bit d/a converter 12.7. usb characteristics 12.8. low - voltage detection characteristics 12.9. flash memory write/erase characteristics 12.10. return time from low - power consumption mode updated 12.4.7. power - on reset timing added the baud rate spec in 12.4.10 csio timing (page 92 , 94 , 96 , 98 ) corrected t he following statement analog port input current ? analog port input leak current i n chapter 12.5. 12 - bit a/d converter ( page 106 ) corrected the part numbers mb9bf528sapmc - ge1 ? mb9bf528sapmc - g k7 e 2 mb9bf529sapmc - ge1 ? mb9bf529sapmc - g k7 e 2 mb9bf528tapmc - ge1 ? mb9bf528tapmc - g k7 e 2 mb9bf529tapmc - ge1 ? mb9bf529tapmc - g k7 e 2 mb9bf528ta bgl - ge1 ? mb9bf528tabgl - g k7 e1 mb9bf529tabgl - ge1 ? mb9bf529tabgl - g k7 e1 in chapter 13. ordering information ( page 121 ) updated 1 4 . package dimensions added 15. errata
document number: 002 - 05661 rev. *d page 130 of 131 mb9b520ta series revision ecn orig. of change submission date description of change *c 5790530 ysat 07/2017/03 adapted new cypress logo *d 6 013729 ysat 01/1 2 /2018 updated arm trademark and the last page updated the figure of lbe192 in 1 4 . package dimensions
document number: 002 - 05661 rev. *d january 12, 2018 page 131 of 131 mb9b520ta series sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you , visit us at cypress locations . products a rm ? cortex ? microcontrollers cypress.com/a rm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot memory cypress.com/memory m icrocontrollers cypress.com/m cu psoc cypress.com/psoc power management ics cypress.com/p mic touch sensing cypress.com/touch usb controllers cypress.com/ usb wireless connectivity cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 mcu cypress developer community c ommunity | projects | video s | blogs | training | co mp onents technical support cypress.com/support a rm and cortex are registered trademarks of a rm limited (or its subsid iaries ) in the u s and /or elsewhere . all other trademarks or registered trademarks referenced herein are the property of their respective owners. ? cypress semiconductor corporation, 2013 - 201 8 . this document is the property of cypress semiconductor corporation and its subsidiaries, including spansion llc (cypress) . this d ocument, including any software or firmware included or referenced in this document (software), is owned by cypress under the intell ectual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under s uch laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, cop yrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do n ot otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non - exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your or ganization, and (b) to distribute the software in binary code form externally to end users (either dir ectly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) under thos e claims of cypresss patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware products. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, exp ress or implied, with regard to this document or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particul ar purpose. no computing device can be absolutely secure. therefore , despite security measures implemented in cypress hardware or software products, cypress does not assume any liability arisi ng out of any security breach, such as unauthorized access to or use of a cypress product. in addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without furth er notice. cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. any informa tion provided in this document, including any sample design information or programming code, is provide d only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test t he functionality and safety of any application made of this information and any resulting product. cypress products are not design ed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life - support devices or systems, other medical devices or systems (including resuscitation equi pment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (unintended uses). a critical component is any component o f a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. cypress is not liable, in whole or in part, and you shall and hereby do release cypress from a ny claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal i njury or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez - usb, f - ram, and traveo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and b rands may be claimed as property of their respective owners.

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